Programmable time advance

Claim 2

A programmable time advance apparatus for a clock generation circuit characterised in that it comprises means (101) for generating a clock signal having a predetermined frequency that is adjustable by the application of control signals to an input control terminal (128); means (140) connected to a reference clock signal (105) for producing a clock adjust signal that is applied to said input control terminal (128) to adjust the frequency of said generated clock signal (105); means (104) for applying a clock advance signal to said generating means (101) concurrent with said clock adjust signal to produce a time offset, advancing said generated clock signal (105).

Claim 3

A circuit according to claim 1, wherein the means (101) for generating a clock signal comprise voltage controlled oscillator means having a predetermined center frequency.

Claim 4

A circuit according to claim l or 2 wherein said applying means (104) comprises: means (136,137) for generating a clock advance signal of predetermined magnitude to produce a fixed time offset to advance said generated clock signal (105).

Claim 5

A circuit according to any preceding claim wherein said applying means (104) further comprises: means (131-135) for periodically applying said clock advance signal to said generating means (101) in synchronization with said reference clock signal (129).

Claim 6

A circuit according to any preceding claim wherein said applying means (104) further includes: means (109) for summing said clock adjust signal and said clock advance signal.

Claim 7

A circuit according to any preceding claim wherein said producing means (140) comprises: phase detector means (110) connected to said signal (105) for generating first/second control signals (V,D) in response to said generated clock signal (105) being less/greater than said reference clock signal (129), respectively.

Claim 8

A circuit according to claim 6 wherein said producing means (140) further comprises: clock adjust signal generating means (108) responsive to said first (V) and second (D) control signals for producing said clock adjust signal of magnitude and polarity indicative of the direction and magnitude of the difference between said reference clock signal (129) and said generated clock signal (105).

Claim 9

A circuit according to claim 7 wherein said clock adjust signal generating means (108) comprises either one or both of the following; (1) first control signal generating means (112, 115, 117) responsive to said first control signal (V) for producing a first difference signal of magnitude and polarity indicative of the direction and magnitude of the difference between said reference clock signal (129) and said generated clock signal (105); (2) second control signal generating means (114, 119, 121) responsive to said second control signal (D) for producing a second difference signal of magnitude and polarity indicative of the direction and magnitude of the difference between said reference clock signal (129) and said generated clock signal (105).

Claim 10

The circuit of claim 8 wherein said producing means (140) further includes: means (116,120) for applying said first/either said first or said second difference signals as said clock adjust signal to said generating means input control terminal (128).

Claim 11

A circuit according to any preceding claim wherein the signals are electrical currents.

Claim 12

A circuit according to claim 10 when appended to claim 8 or 9 wherein the control signal generating means (112, 114, 115, 117, 121, 122) converts the duration of said first/second control signals (V,D) into a difference current of duration proportional to the first/second control signal duration.

Claim 15

The method of claim 12 wherein said step of combining further comprises the step of: periodically applying said clock advance signal to said input control terminal (128) in synchronization with said reference clock signal (129).