EP0352111A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Oki Electric Industry Co Ltd
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Filing: 1989-07-20
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Granted: —
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Expires: 2009-07-20
Abstract
Abstract A MOS semiconductor memory device comprising a memory matrix having semiconductor memory elements (M1a...M1x; M2a...M2x) arranged in rows and columns, in which the memory elements in each row are connected to respective word lines (11a, 11b), and the memory elements in the columns are being connected to respective source lines (12a...12f; 16a...16f) and data lines (13a...13f; 17a...17f). A row decoder (60) outputs a row selection signal (Y) to one of the rows of the memory elements through the word lines, while a column decoder (62) outputs a column selection signal to one the columns through the source lines (12, 16). A common data line (42, 44; 52, 54) is electrically coupled to a plurality of the data lines, a constant voltage is applied from a common circuit (46a, 46b; 56a, 56b) to the data lines through the common data line, and the current reguired for maintaining the common data line at a constant voltage is detected by a detecting circuit (46a, 46b; 56a, 56b).
Inventors
- 👤 Shooji Oki Electric Industry Co. Ltd. Kitazawa
- 👤 Teruhiro Oki Electric Industry Co. Ltd. Harada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 05:42
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/26; G11C16/30
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
164 words
A MOS semiconductor memory device comprising: a memory matrix having semiconductor memory elements arranged in rows and columns; a plurality of word lines connected to the semiconductor memory elements arranged in the same rows; a row decoder for outputting a row selection signal to one of the rows of the semiconductor memory elements through the word lines; a plurality of source lines connected to the semiconductor memory elements arranged in the same columns; a column decoder for outputting a column selection signal to one of the columns of the semiconductor memory elements through said source lines; a plurality of data lines connected to the semiconductor memory elements arranged in the same columns; a common data line electrically coupled to a plurality of the data lines; a constant voltage applying means for applying a constant voltage to the data lines through the common data line; and a current detecting means for detecting the current required for maintaining the common data line at a constant voltage.
Claim 2
Dependent Claim
164 words
A MOS semiconductor memory device comprising: a memory matrix having semiconductor memory elements arranged in rows and columns; a plurality of word lines connected to the semiconductor memory elements arranged in the same rows; a row decoder for outputting a row selection signal to one of the rows of the semiconductor memory elements through the word lines; a plurality of source lines connected to the semiconductor memory elements arranged in the same columns; a column decoder for outputting a column selection signal to one of the columns of the semiconductor memory elements through said source lines; a plurality of data lines connected to the semiconductor memory elements arranged in the same columns; a common data line electrically coupled to a plurality of the data lines; a constant voltage applying means for applying a constant voltage to the data lines through the common data line; and a current detecting means for detecting the current required for maintaining the common data line at a constant voltage.
Claim 3
Dependent Claim
20 words
A MOS semiconductor memory device according to claim 1, wherein the data lines have an electrical resistor connected in series.
Claim 4
Dependent Claim
19 words
A MOS semiconductor memory device according to claim 2, wherein said electrical resistor is formed of a resistive material.
Claim 5
Dependent Claim
25 words
A MOS semiconductor memory device according to claim 2, wherein said electrical resistor is formed of a MOS transistor with its gate potential being fixed.
Claim 6
Dependent Claim
55 words
A MOS semiconductor memory device according to claim 1, further comprising a constant voltage generating means, and causes, on the basis of the voltage generated from the constant voltage generating means, generation of both the voltage applied to the source lines and the voltage applied from the constant voltage applying means to the data lines.
Claim 7
Dependent Claim
35 words
A MOS semiconductor memory device according to claim 5, further comprising wiring conductors connecting the constant voltage applying means, and wherein said constant voltage applying means is provided with another wiring layer for electrical shield.
Claim 8
Dependent Claim
62 words
A MOS semiconductor memory device according to claim 1, further comprising: a plurality of switch means respectively connected in series with the source lines; and a block decoder for controlling the operation of the switch means; wherein said column decoder outputs the column select signal to one of the columns of the semiconductor memory elements, said switch means and said source lines.
Claim 9
Dependent Claim
60 words
A MOS semiconductor memory device according to claim 7, wherein said switch means comprises a MOS transistor, a first electrode of this MOS transistor is connected to the wiring conductor, a second electrode of this MOS transistor is connected to the source line, and the gate of the MOS transistor is connected to the output terminal of the block decoder.
Claim 10
Dependent Claim
154 words
A semiconductor memory device comprising a memory matrix having semiconductor memory elements (M1a...M1x; M2a...M2x) arranged in rows and columns; means (60) for selecting aparticular row of the memory elements; a plurality of source lines (12a...12f; 16a...16f) connected to said columns of elements; a column decoder (62) for outputting a column selection signal to a particular column of said memory elements through the source lines (12, 16); a plurality of data lines (13a...13f; 17a...17f) connected to said columns of memory elements to receive a data signal from a selected row and column location thereof; and reference voltage applying means (70) for applying a reference voltage to the data lines; characterised by said data lines being coupled in a group to a common data line (42, 44; 52, 54) and means (46a, 46b; 56a, 56b) responsive to the current flowing in the common data line to maintain said common data line at a given reference voltage.
Claim 11
Dependent Claim
154 words
A semiconductor memory device comprising a memory matrix having semiconductor memory elements (M1a...M1x; M2a...M2x) arranged in rows and columns; means (60) for selecting aparticular row of the memory elements; a plurality of source lines (12a...12f; 16a...16f) connected to said columns of elements; a column decoder (62) for outputting a column selection signal to a particular column of said memory elements through the source lines (12, 16); a plurality of data lines (13a...13f; 17a...17f) connected to said columns of memory elements to receive a data signal from a selected row and column location thereof; and reference voltage applying means (70) for applying a reference voltage to the data lines; characterised by said data lines being coupled in a group to a common data line (42, 44; 52, 54) and means (46a, 46b; 56a, 56b) responsive to the current flowing in the common data line to maintain said common data line at a given reference voltage.
References Cited (Backward Citations)
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