Floating point arithmetic units

Claim 2

A floating point arithmetic unit, for executing an iterative binary arithmetic operation upon two operands (D₁, D₂) applied to the unit in floating point form, which unit includes respective operating portions for deriving mantissa, exponent and sign components of the desired result (D₃) respectively, the mantissa operating portion including fixed point multiplication means (10) for multiplying together the respective mantissa components of the two operands concerned; characterised in that the mantissa operating portion further includes subtraction means (41, 42, 15) operative, in each cycle of the iterative operation, to form the inverse of the fractional part of a binary number derived from the output of the said multiplication means (10) and to increment that inverse by adding one to the least significant bit thereof.

Claim 3

A floating point operation unit comprising an exponent operation means for operating exponents from two inputs to be operated, a sign operation means for operating signs from the two inputs, and a mantissa operation means for operating mantissas from the two inputs; the mantissa operation means comprising: a fixed point multiplication means for multiplying one of the mantissas with another of the mantissas; a first right shift means receiving an output of the fixed point multiplication means for normalizing the output; an incrementer means receiving an output of the first right shift means; a rounding off control means receiving the output of the first right shift means, and supplying the output thereof to the incrementer means; a second right shift means receiving a carry signal of the incrementer means, and for shifting the output of the incrementer means to the right when the carry signal is supplied; and an inversion means receiving the output of the first right shift means, for selectively supplying an inverting output to the incrementer means instead of the output of the first right shift means when one operation of an iterative approximation in a division or a square root operation is executed; the incrementer means being supplied with the increment signal when the respective one operation of the iterative approximation is executed; the second right shift means shifting the output of the incrementer means to the right when the one operation of the iterative approximation of the square root operation is executed.

Claim 4

A floating point operation unit comprising an exponent operation means for operating exponents from two inputs to be operated, a sign operation means for operating signs from the two inputs, and a mantissa operation means for operating mantissas from the two inputs; the mantissa operation means comprising: a fixed point multiplication means for multiplying one of the mantissas with another of the mantissas; a first right shift means receiving an output of the fixed point multiplication means for normalizing the output; an incrementer means receiving an output of the first right shift means; a rounding off control means receiving the output of the first right shift means, and supplying the output thereof to the incrementer means; a second right shift means receiving a carry signal of the incrementer means, and for shifting the output of the incrementer means to the right when the carry signal is supplied; and an inversion means receiving the output of the first right shift means, for selectively supplying an inverting output to the incrementer means instead of the output of the first right shift means when one operation of an iterative approximation in a division or a square root operation is executed; the incrementer means being supplied with the increment signal when the respective one operation of the iterative approximation is executed; the second right shift means shifting the output of the incrementer means to the right when the one operation of the iterative approximation of the square root operation is executed.

Claim 5

A floating point operation unit as set forth in claim 2, wherein the fixed multiplication means comprises a partial products multiplier and addition circuit, and another adder, and a carry of the another adder is supplied to the first right shift means to shift the output of the fixed point multiplication means by one bit to the right.

Claim 6

A floating point operation unit as set forth in claim 2, wherein the mantissa operation means further comprises a multiplexer between the inverter means and the incrementer means, so that the multiplexer selects the output of the first right shift means when the control signal for the respective one operation of the iterative approximation in the division and the square root operation is not given and selects the output of the inversion means when the control signal is given.

Claim 7

A floating point operation unit comprising an exponent operation means for operating exponents from two inputs to be operated, a sign operation means for operating signs from the two inputs, and a mantissa operation means for operating mantissas from the two inputs; the mantissa operation means comprising: a fixed point multiplication means for multiplying one of the mantissas with another of the mantissas; a first right shift means receiving an output of the fixed point multiplication means for normalizing the output; an incrementer means receiving an output of the first right shift means; a round control means receiving the output of the first right shift means, and supplying the output thereof to the incrementer means; a second right shift means receiving a carry signal of the incrementer means, and for shifting the output of the incrementer means to the right when the carry signal is supplied; and an inversion means receiving the output of the first right shift means, for selectively supplying an output thereof put to the incrementer means instead of the output of the first right shift means, when one operation of an iterative approximation in a square root operation is executed, and the output of the inversion means that all bits below a point in binary notation are inverted and all bits over the point, "10" are set; the incrementer means being supplied with the increment signal when the one operation of the iterative approximation in the square root operation is executed.

Claim 8

A floating point operation unit comprising an exponent operation means for operating exponents from two inputs to be operated, a sign operation means for operating signs from the two inputs, and a mantissa operation means for operating mantissas from the two inputs; the mantissa operation means comprising: a fixed point multiplication means for multiplying one of the mantissas with another of the mantissas; a first right shift means receiving an output of the fixed point multiplication means for normalizing the output; an incrementer means receiving an output of the first right shift means; a round control means receiving the output of the first right shift means, and supplying the output thereof to the incrementer means; a second right shift means receiving a carry signal of the incrementer means, and for shifting the output of the incrementer means to the right when the carry signal is supplied; and an inversion means receiving the output of the first right shift means, for selectively supplying an output thereof put to the incrementer means instead of the output of the first right shift means, when one operation of an iterative approximation in a square root operation is executed, and the output of the inversion means that all bits below a point in binary notation are inverted and all bits over the point, "10" are set; the incrementer means being supplied with the increment signal when the one operation of the iterative approximation in the square root operation is executed.