EP0348654A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method and apparatus for increasing system throughput
Assignee: International Business Machines Corp
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Filing: 1989-05-17
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Granted: —
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Expires: 2009-05-17
Abstract
Abstract In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the input/output interface controller (IOIC) is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The storage controller (SC) is connected to a common system memory and possibly also to an insturction processing unit. The SPD bus, which comprises three sub-buses and a control bus, conducts signals between each input/output processor (IOP) and the input/output interface controller (IOIC) in an asynchronous "handshaking" manner. The adapter bus, which comprises two sub-buses and a control bus, conducts signals between the input/output interface controller (IOIC) and the storage controller (SC) in a synchronous manner. The input/output interface controller (IOIC), interconnected between the SPD bus and adapter bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. The input/output interface controller (IOIC) also comprises at least one shared DMA facility for executing DMA storage operations requested by the input/output processors (IOP's) via the SPD bus. Each shared DMA facility includes a buffer for control information and data to be transmitted between the storage controller (SC) and one of the input/output processors (IOP's) and a bus interface coupled to the buffer, to the adpater bus and to the SPD bus for independently transferring the control information and data between the buffer and the storage controller (SC), on one hand, via the adapter bus, and between the buffer and the one input/output processor (IOP), on the other hand, via the SPD bus. In this manner, the SPD bus can be released for utilization by other input/output processors (IOP's) connected thereto during a period of "storage latency" after a DMA storage operation has been initiated by one input/output processor (IOP).
Inventors
- 👤 Douglas Roderick Chisholm
- 👤 Robert Garis Iseminger
- 👤 Richard Allen Kelley
- 👤 Wan Lin Leung
- 👤 James Theodore Moyer
- 👤 Mark Carl Snedaker
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 03:19
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
285 words
Computer system capable of executing direct memory access (DMA) storage operations between a common memory and a plurality of data sources, characterized by a combination of: a common memory for storing data at a plurality of addressable memory locations; a storage controller, coupled to said memory, for executing DMA storage operations with respect to said memory locations in response to DMA requests received from said sources; an "SPD" input/output bus; a plurality of input/output processors (IOP's), coupled to said SPD bus, for issuing DMA storage operation requests to transfer data to, or receive data from, prescribed locations in said memory; and an input/output interface controller (IOIC), coupled between said storage controller and said SPD bus, including means for communicating with said storage controller in behalf of said input/output processors (IOP's) to transfer control information and data between said memory and said input/output processors (IOP's); the input/output interface controller (IOIC) comprising at least one shared DMA facility for executing a plurality of DMA storage operations requested by said input/output processors (IOP's) via said SPD bus, each shared DMA facility including: (1) means for buffering control information and data to be transmitted between said storage controller and one of said input/output processors (IOP's); and (2) interface means, coupled to said buffering means, said storage controller and to said SPD bus, for independently transferring control information and data between said buffer means and said storage controller, on one hand, and between said buffering means and said one input/output processor (IOP), in the other hand, whereby said SPD bus is released for utilization by other input/output processors (IOP's) connected thereto during a period of storage latency after a DMA storage operation has been initiated by one input/output processor (IOP).
Claim 2
Dependent Claim
285 words
Computer system capable of executing direct memory access (DMA) storage operations between a common memory and a plurality of data sources, characterized by a combination of: a common memory for storing data at a plurality of addressable memory locations; a storage controller, coupled to said memory, for executing DMA storage operations with respect to said memory locations in response to DMA requests received from said sources; an "SPD" input/output bus; a plurality of input/output processors (IOP's), coupled to said SPD bus, for issuing DMA storage operation requests to transfer data to, or receive data from, prescribed locations in said memory; and an input/output interface controller (IOIC), coupled between said storage controller and said SPD bus, including means for communicating with said storage controller in behalf of said input/output processors (IOP's) to transfer control information and data between said memory and said input/output processors (IOP's); the input/output interface controller (IOIC) comprising at least one shared DMA facility for executing a plurality of DMA storage operations requested by said input/output processors (IOP's) via said SPD bus, each shared DMA facility including: (1) means for buffering control information and data to be transmitted between said storage controller and one of said input/output processors (IOP's); and (2) interface means, coupled to said buffering means, said storage controller and to said SPD bus, for independently transferring control information and data between said buffer means and said storage controller, on one hand, and between said buffering means and said one input/output processor (IOP), in the other hand, whereby said SPD bus is released for utilization by other input/output processors (IOP's) connected thereto during a period of storage latency after a DMA storage operation has been initiated by one input/output processor (IOP).
Claim 3
Dependent Claim
64 words
Computer system as defined in claim 1, characterized in that the input/output interface controller (IOIC) comprises a plurality of said shared DMA facilities, each DMA facility being operative to implement a DMA storage operation request issued by one input/output processor (IOP) on said SPD bus, different ones of said DMA facilities being operative to concurrently serve different ones of said input/output processors (IOP's), respectively.
Claim 4
Dependent Claim
31 words
Computer system as defined in claim 2, characterized in that the input/output processors (IOP's) each include means for requesting that a shared DMA facility be allocated to a DMA storage operation.
Claim 5
Dependent Claim
58 words
Computer system as defined in claim 1, characterized in that the input/output processors (IOP's) each include means for transmitting a DMA initialization unit operation message from said input/output processor (IOP) to said associated input/output interface controller (IOIC), said message comprising address and control information sufficient to permit said input/output interface controller (IOIC) to execute a DMA storage operation.
Claim 6
Dependent Claim
31 words
Computer system as defined in claim 1, characterized in that the buffering means of said DMA facility includes means for buffering one packet of data, wherein the packet comprises 64 bytes.
Claim 7
Dependent Claim
36 words
Computer system as defined in claim 1, characterized in that each of said input/output processors (IOP's) comprises a plurality of ports, said at least one input/output processor (IOP) having and address which includes a port number.
Claim 8
Dependent Claim
57 words
Computer system as defined in claim 1, characterized by a plurality of said SPD buses and a plurality of input/output interface controllers (IOIC'S), each SPD bus being connected to a separate one of said input/output interface controllers (IOIC'S), and further comprising an "adapter" bus coupled between all of said input/output interface controllers (IOIC'S) and said storage controller.
Claim 9
Dependent Claim
38 words
Computer system as defined in claim 1, characterized by an instruction processing unit (IPU) and a "memory" bus coupled between said instruction processing unit (IPU) and said storage controller, on one hand, and said memory, on the other.
Claim 10
Dependent Claim
101 words
Computer system as defined in claim 1, characterized in that the input/output interface controller (IOIC) comprises a plurality of said shared DMA facilities for executing a plurality of DMA storage operations in time overlapping relationship, each DMA facility being allocated to execute one DMA storage operation at a time; further comprising first multiple or means, coupled between said SPD bus, on the one hand, and said interface means of each DMA facility, on the other, for selecting a DMA facility for use with said one input/output processor (IOP) upon request by such input/output processor (IOP) to execute a DMA storage operation.
Claim 11
Dependent Claim
184 words
Method of executing a DMA storage read (remote write) operation to read data from prescribed locations in said memory and to transfer said data to one of said input/output processors (IOP's), for operating in a computer system according claim 1, characterized by the steps of: (1) transmitting a DMA initialization unit operation message from said one input/output processor (IOP) to said input/output interface controller (IOIC) via said SPD bus, said message containing the address of said prescribed locations in memory and the address of said one input/output processor (IOP); (2) releasing said SPD bus for transmission of control information and data to and from other input/output processors (IOP's) connected thereto; (3) reading a packet of said requested data from said prescribed locations in memory; (4) transmitting said packet of data from said storage controller to said input/output interface controller (IOIC); (5) storing said packet of data in said input/output interface controller (IOIC); (6) requesting and obtaining use of said SPD bus; and (7) transmitting said packet of data from said input/output interface controller (IOIC) to said one input/output processor (IOP) via said SPD bus.
Claim 12
Dependent Claim
75 words
Method as defined in claim 10, characterized by the step of signalling a stop from said one input/output processor (IOP) to said input/output interface controller (IOIC), thereby terminating the transmission of further packets of data to said one input/output processor (IOP), and a step of signalling a stop from said input/output interface controller (IOIC) to said one input/output processor (IOP), thereby terminating the transmission of further packets of data to said one input/output processor (IOP).
Claim 13
Dependent Claim
152 words
Method as defined in claim 10, characterized by the steps of: (1) transmitting a DMA initialization unit operation message from said one input/output processor (IOP) to said input/output interface controller (IOIC) via said SPD bus, said message containing the memory address of the data to be written and the address of said one input/output processor (IOP); (2) issuing a request for data from said input/output interface controller (IOIC) to said one input/output processor (IOP) via said SPD bus; (3) transmitting a first packet of said data from said one input/output processor (IOP) to said input/output interface controller (IOIC) via said SPD bus upon receipt of said request for data; (4) releasing said SPD bus for transmission of control information and data to and from other input/output processors (IOP's) connected thereto; and (5) transmitting said first packet of data from said input/output interface controller (IOIC) to said storage controller for storage in memory.
Claim 14
Dependent Claim
70 words
Method as defined in claim 12, further comprising the steps of: (6) writing said packet of data into the addressed locations in memory; (7) transmitting status signals from said storage controller to said input/output interface controller (IOIC) indicating whether such DMA storage write operation has been successfully completed; and (8) transmitting said status information from said input/output interface controller (IOIC) to said one input/output processor (IOP) via said SPD bus.
Claim 15
Dependent Claim
88 words
Method as defined in claim 13, further comprising the steps of: (9) transmitting a second packet of data from said one input/output processor (IOP) to said input/output interface controller (IOIC) via SPD bus upon receipt of said status information by said one input/output processor (IOP); (10) releasing said SPD bus for transmission of control information and data to and from other input/output processors (IOP's) connected thereto; and (11) transmitting said second packet of data from said input/output interface controller (IOIC) to said storage controller for storage in memory.
Claim 16
Dependent Claim
156 words
Computer system as defined in claim 1, characterized by an improvement wherein said input/output interface controller (IOIC) further comprises at least one shared DMA facility for executing DMA storage operations requested by said input/output processors (IOP's) via said SPD bus, and wherein each input/output processor (IOP) comprises means for transmitting, to said DMA facility, a DMA initialization unit operation message thereby to commence a DMA storage operation to transfer data from prescribed locations in said memory to said one input/output processor (IOP) or to transfer data from said one input/output processor (IOP) tor prescribed locations in said memory, said DMA initialization unit operation message comprising the following information: (1) the type of DMA storage operation (read or write); (2) the input/output processor (IOP) address on said SPD bus; (3) the maximum size of a packet of data to be transferred; (4) the DMA byte count; and (5) the memory address of the data to be transferred.
Claim 17
Dependent Claim
16 words
Computer system as defined in claim 15, characterized in that the memory address comprises 32 bits.
Claim 18
Dependent Claim
18 words
Computer system as defined in claim 15, characterized in that the memory address comprises more than 32 bits.
Claim 19
Dependent Claim
33 words
Computer system as defined in claim 15, characterized in that the DMA initialization unit operation message further comprises an auxiliary storage select bit; address limit mode checking control bits; and storage key bits.
References Cited (Backward Citations)
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