EP0348045A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method of controlling the operating speed of an information processing unit, and related information processing unit
Assignee: Seiko Epson Corp
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Filing: 1989-05-25
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Granted: —
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Expires: 2009-05-25
Abstract
Abstract An information processing unit has a central processing unit (1) and means (3, 4, 5; 3, 4, 5A; 3, 10; 40) for generating clock pulses (CLK) for supply to a clock input terminal of the central processing unit for controlling the timing of the central processing unit. The frequency of the clock pulses is arranged to be altered for selectively varying this timing, for example in dependence upon the current operation of a bus cycle of the central processing unit, addresses to be accessed by the central processing unit, ambient temperature or line voltage.
Inventors
- 👤 Koji Takeda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 14:13
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F1/00; G06F1/04; G06F1/08
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
59 words
A method of controlling the operating speed of an information processing unit including a central processing unit, comprising generating clock pulses (CLK) for supply to a clock input terminal of the central processing unit (1) for controlling the timing of the central processing unit, and characterised by altering the frequency of the clock pulses for selectively varying the timing.
Claim 2
Independent Claim
59 words
A method of controlling the operating speed of an information processing unit including a central processing unit, comprising generating clock pulses (CLK) for supply to a clock input terminal of the central processing unit (1) for controlling the timing of the central processing unit, and characterised by altering the frequency of the clock pulses for selectively varying the timing.
Claim 3
Dependent Claim
30 words
A method according to claim 1 characterised by altering the frequency of the clock pulses in dependence upon the current operation within a bus cycle of the central processing unit.
Claim 4
Dependent Claim
30 words
A method according to claim 2 characterised in that the duration of read and write bus operations in a memory are controlled by altering the frequency of the clock pulses.
Claim 5
Independent Claim
29 words
A method according to any preceding claim characterised by altering the frequency of the clock pulses in dependence upon respective addresses to be accessed by the central processing unit.
Claim 6
Independent Claim
22 words
A method according to any preceding claim characterised by altering the frequency of the clock pulses in dependence upon the ambient temperature.
Claim 7
Independent Claim
21 words
A method according to any preceding claim characterised by altering the frequency of the clock pulses in dependence upon line voltage.
Claim 8
Dependent Claim
40 words
A method according to claim 2 or 3 characterised by altering the frequency of the clock pulses during a respective bus operation by extending the period of a selected number of the clock pulses occurring during the respective bus operation.
Claim 9
Dependent Claim
14 words
A method according to claim 7 characterised in that the selected number is pre-programmed.
Claim 10
Dependent Claim
35 words
A method according to claim 7 or 8 further characterised by extending the overall number of clock pulses in the respective bus operation so as to generate a wait step in the central processing unit.
Claim 11
Dependent Claim
91 words
An information processing unit having a central processing unit (1), and means (3, 4, 5; 3, 4, 5A; 3, 10) for generating clock pulses (CLK) for supply to a clock input terminal of the central processing unit for controlling the timing of the central processing unit, characterised in that the means for generating the clock pulses comprise means (3) for generating an oscillating signal, and means (4, 5; 4, 5A; 10) for variably dividing the frequency of the oscillating signal so as to generate clock pulses having a selectively variable frequency.
Claim 12
Dependent Claim
91 words
An information processing unit having a central processing unit (1), and means (3, 4, 5; 3, 4, 5A; 3, 10) for generating clock pulses (CLK) for supply to a clock input terminal of the central processing unit for controlling the timing of the central processing unit, characterised in that the means for generating the clock pulses comprise means (3) for generating an oscillating signal, and means (4, 5; 4, 5A; 10) for variably dividing the frequency of the oscillating signal so as to generate clock pulses having a selectively variable frequency.
References Cited (Backward Citations)
No citation records indexed.
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