Semiconductor memory device

Claim 2

A semiconductor memory device characterized by comprising: row lines (WL1,..., WLm); memory cells (MC11,... MCmn) selected by said row lines; column lines (BL1,..., Bln) receiving data from said memory cells; a first load circuit (14A) coupled with said column lines; first dummy cells (DC1,..., DCm) selected by said row lines; a dummy column line (DBL) to which said first dummy cells are connected; a second load circuit (14B) connected to said dummy column line; a second dummy cell (DCm+1) connected to said dummy column line and supplied at the gate with a preset potential; and a sense amplifier (15) for sensing the data stored in said memory cell in accordance with a potential difference between said column line and said dummy column line.

Claim 3

A semiconductor memory device characterized by comprising: row lines (WL1,..., WLm); memory cells (MC11,..., MCmn) selected by said row lines; column lines (BL1,..., BLn) receiving data from said memory cells; a first load circuit (14A) coupled with said column lines; first dummy cells (DC1,..., DCm) selected by said row lines; a dummy column line (DBL) to which said first dummy cells are connected; a second load circuit (14B) connected to said dummy column line; a pulse signal generating circuit (18) for generating a pulse signal by detecting a change in an address input signal; a second dummy cell (DCm+1) connected to said dummy column line and controlled in conduction by said pulse signal generated by said pulse signal generating circuit; and a sense amplifier (15) for sensing the data stored in said memory cell in accordance with a potential difference between said column line and said dummy column line.

Claim 4

A semiconductor memory device characterized by comprising: row lines (WL1,..., WLm); memory cells (MC11,..., MCmn) selected by said row lines; column lines (BL1,..., BLn) receiving data from said memory cells; a first load circuit (14A) coupled with said column lines; first dummy cells (DC1,..., DCm) selected by said row lines; a dummy column line (DBL) to which said first dummy cells are connected; a second load circuit (14B) connected to said dummy column line; a pulse signal generating circuit (18) for generating a pulse signal by detecting a change in an address input signal; a second dummy cell (DCm+1) connected to said dummy column line and controlled in conduction by said pulse signal generated by said pulse signal generating circuit; and a sense amplifier (15) for sensing the data stored in said memory cell in accordance with a potential difference between said column line and said dummy column line.

Claim 5

A semiconductor memory device characterized by comprising: row lines (WL1,..., WLm); memory cells (MC11,..., MCmn) selected by said row lines; column lines (BL1,..., BLn) receiving data from said memory cells; a first load circuit (14A) coupled with said column lines; first dummy cells (DC1,..., DCm) selected by said row lines; a dummy column line (DBL) to which said first dummy cells are connected; a pulse signal generating circuit (18) for generating a pulse signal by detecting a change in an address input signal; a second load circuit (14B) connected to said dummy column line, a conduction resistance of said second load circuit being controlled by a pulse signal generated by said pulse signal generating circuit; and a sense amplifier (15) for sensing the data stored in said memory cell in accordance with a potential difference between said column line and said dummy column line.

Claim 6

A semiconductor memory device characterized by comprising: row lines (WL1,..., WLm); memory cells (MC11,..., MCmn) selected by said row lines; column lines (BL1,..., BLn) receiving data from said memory cells; a first load circuit (14A) coupled with said column lines; first dummy cells (DC1,..., DCm) selected by said row lines; a dummy column line (DBL) to which said first dummy cells are connected; a pulse signal generating circuit (18) for generating a pulse signal by detecting a change in an address input signal; a second load circuit (14B) connected to said dummy column line, a conduction resistance of said second load circuit being controlled by a pulse signal generated by said pulse signal generating circuit; and a sense amplifier (15) for sensing the data stored in said memory cell in accordance with a potential difference between said column line and said dummy column line.

Claim 7

A semiconductor memory device according to claim 1, characterized in that said predetermined potential is a power source voltage.

Claim 8

A semiconductor memory device according to claim 1, characterized in that said predetermined potential is a potential different from a power source voltage.

Claim 9

A semiconductor memory device according to claim 3, characterized in that said second load circuit (14B) includes first and second MOSFETs (QD7a, QD7b) connected in parallel between a power source and said dummy column line, the gate of said first MOSFET (QD7a) is connected to said dummy column line, and the gate of said second MOSFET (QD7b) is coupled for reception with said pulse signal outputted from said pulse signal generating circuit.

Claim 10

A semiconductor memory device characterized by comprising: at least one memory cell (MC11,..., MCmn); a first MOS transistor (QM1) having a source-drain current path, one end of said source-drain current path being connected to a drain of said memory cell, the other end of said source-drain current path being connected to a data sensing node which potential varies according to a stored data in said memory cell, and said first MOS transistor receiving at the gate a first bias voltage; a load circuit (14A) for controlling a current flowing through said memory cell, said load circuit including a first load means (QM7B) for determining a potential of said sensing node by limiting a load current flowing through said load circuit and operating as a substantially constant current source when said memory cell is conductive, and said load circuit (QM7A) including a second load means for setting a potential of said sensing node below a potential of said first power source when said memory cell is nonconductive; a sense circuit (15) for reading out the data from said memory cell, said sense circuit being connected to said sensing node.

Claim 11

A semiconductor memory device characterized by comprising: at least one memory cell (MC11,..., MCmn); a first MOS transistor (QM1) having a source-drain current path, one end of said source-drain current path being connected to a drain of said memory cell, the other end of said source-drain current path being connected to a data sensing node which potential varies according to a stored data in said memory cell, and said first MOS transistor receiving at the gate a first bias voltage; a load circuit (14A) for controlling a current flowing through said memory cell, said load circuit including a first load means (QM7B) for determining a potential of said sensing node by limiting a load current flowing through said load circuit and operating as a substantially constant current source when said memory cell is conductive, and said load circuit (QM7A) including a second load means for setting a potential of said sensing node below a potential of said first power source when said memory cell is nonconductive; a sense circuit (15) for reading out the data from said memory cell, said sense circuit being connected to said sensing node.

Claim 12

A semiconductor memory device characterized by comprising: at least one memory cell (MC11,..., MCmn); a first MOS transistor (QM1) having a source-drain current path, one end of said source-drain current path being connected to a drain of said memory cell, the other end of said source-drain current path being con­nected to a data sensing node which potential varies according to a stored data in said memory cell, and said first MOS transistor receiving at the gate a first bias voltage; a load circuit (14A) for controlling a current flowing through said memory cell, said load circuit being connected between said data sensing node and a first power source, said load circuit having a first load transistor (QM7B) for determining a potential of said sensing node by limiting a load current flowing through said load circuit when said memory cell is conductive, and a potential difference between a gate and a source of said first load transistor being independent of the potential of said sensing node, said load circuit having a second load transistor (QM7A) for setting a potential of said sensing node below a potential of said first power source when said memory cell is nonconductive and a potential difference between a gate and a source of said second load transistor being depend on the potential of said sensing node; a sense circuit (15) for reading out the data from said memory cell, said sense circuit being connected to said sensing node.

Claim 13

A semiconductor memory device characterized by comprising: at least one memory cell (MC11,..., MCmn); a first MOS transistor (QM1) having a source-drain current path, one end of said source-drain current path being connected to a drain of said memory cell, the other end of said source-drain current path being con­nected to a data sensing node which potential varies according to a stored data in said memory cell, and said first MOS transistor receiving at the gate a first bias voltage; a load circuit (14A) for controlling a current flowing through said memory cell, said load circuit being connected between said data sensing node and a first power source, said load circuit having a first load transistor (QM7B) for determining a potential of said sensing node by limiting a load current flowing through said load circuit when said memory cell is conductive, and a potential difference between a gate and a source of said first load transistor being independent of the potential of said sensing node, said load circuit having a second load transistor (QM7A) for setting a potential of said sensing node below a potential of said first power source when said memory cell is nonconductive and a potential difference between a gate and a source of said second load transistor being depend on the potential of said sensing node; a sense circuit (15) for reading out the data from said memory cell, said sense circuit being connected to said sensing node.

Claim 14

A semiconductor memory device according to claim 8, characterized in that said first load tran­sistor (QM7B) is a p-channel MOS transistor biased at the gate by a fixed voltage lower than a voltage of said power source, and said second load transistor (QM7A) is a p-channel MOS transistor having the gate connected to said sensing node.

Claim 15

A semiconductor memory device according to claim 9, characterized in that said second load transistor (QM7A) has a larger transconductance than that of said first load transistor.

Claim 16

A semiconductor memory device according to claim 8, characterized in that said first load tran­sistor in said load circuit is an n-channel MOS tran­sistor (QM8) whose gate and source are interconnected, and whose threshold voltage is negative.

Claim 17

A semiconductor memory device according to claim 8, characterized in that said second load tran­sistor in said load circuit is an n-channel MOS transistor (QM9) biased at the gate by a voltage of said first power source, and having a positive threshold voltage.

Claim 18

A semiconductor memory device according to claim 8, characterized in that said first load transistor (QM7B) in said load circuit is a p-channel MOS transistor receiving at the gate an internal control signal ( CE′ ) which is set at a ground potential in response to an external control signal when said memory device is in an active mode, and is set at the potential of said first power source when said memory device is in a stand-by mode.

Claim 19

A semiconductor memory device according to claim 8, characterized in that said second load transistor in said load circuit is an n-channel MOS transistor receiving at the gate an internal control signal ( CE′ ) which is set at the potential of said first power source in response to an external control signal when said memory device is in an active mode, and is set at the ground potential when said memory device is in a stand-by mode.

Claim 20

A semiconductor memory device characterized by comprising: row lines (WL1,..., WLm); memory cells (MC11,..., MCmn) selected by said row lines; column lines (BL1,..., BLn) receiving data from said memory cells; a data sensing node; a first bias potential setting circuit (13A) including first and second MOS transistors (QM1, QM4), said first MOS transistor (QM1) being connected between said memory cells and said data sensing node, and receiving at the gate a first bias voltage, said second MOS transistor (QM4) connected between said memory cells and a power source, and receiving at the gate a second bias voltage lower than said first bias voltage; a first load circuit (14A) for controlling a current flowing through said memory cell, said load circuit being connected between said data sensing node and a first power source, said load circuit having a first load transistor (QM7B) for determining a potential of said sensing node by limiting a load current flowing through said load circuit when said said memory cell is conductive, and a potential difference between a gate and a source of said first load transistor being independent of the potential of said sensing node, said load circuit having a second load transistor (QM7A) for setting a potential of said sensing node below a potential of said first power source when said memory cell is nonconductive and a potential difference between a gate and a source of said second load transistor being dependent on the potential of said sensing node; first dummy cells (DC1,..., DCm) selected by said row lines; a dummy column line (DBL) to which said first dummy cells are connected; a second dummy cell (DCm+1) connected to said dummy column line and supplied at the gate with a preset potential; a reference potential node (B); a second bias potential setting circuit (13B) including third and fourth MOS transistors (QD1, QD4), said third MOS transistor (QD1) being connected between said first and second dummy cells and said reference potential node and receiving at the gate a third bias voltage, said fourth MOS transistor (QD4) connected between said first and second dummy cells and a power source and receiving at the gate a fourth bias voltage lower than said third bias voltage; a second load circuit (14B) connected in series between said reference potential node and said first power source for controlling a current flowing through said first and second dummy cells; and a sense amplifier (15) for sensing the data stored in said memory cell in accordance with a potential difference between said reference potential node and said data sensing node.

Claim 21

A semiconductor memory device characterized by comprising: row lines (WL1,..., WLm); memory cells (MC11,..., MCmn) selected by said row lines; column lines (BL1,..., BLn) receiving data from said memory cells; a data sensing node; a first bias potential setting circuit (13A) including first and second MOS transistors (QM1, QM4), said first MOS transistor (QM1) being connected between said memory cells and said data sensing node, and receiving at the gate a first bias voltage, said second MOS transistor (QM4) connected between said memory cells and a power source, and receiving at the gate a second bias voltage lower than said first bias voltage; a first load circuit (14A) for controlling a current flowing through said memory cell, said load circuit being connected between said data sensing node and a first power source, said load circuit having a first load transistor (QM7B) for determining a potential of said sensing node by limiting a load current flowing through said load circuit when said said memory cell is conductive, and a potential difference between a gate and a source of said first load transistor being independent of the potential of said sensing node, said load circuit having a second load transistor (QM7A) for setting a potential of said sensing node below a potential of said first power source when said memory cell is nonconductive and a potential difference between a gate and a source of said second load transistor being dependent on the potential of said sensing node; first dummy cells (DC1,..., DCm) selected by said row lines; a dummy column line (DBL) to which said first dummy cells are connected; a second dummy cell (DCm+1) connected to said dummy column line and supplied at the gate with a preset potential; a reference potential node (B); a second bias potential setting circuit (13B) including third and fourth MOS transistors (QD1, QD4), said third MOS transistor (QD1) being connected between said first and second dummy cells and said reference potential node and receiving at the gate a third bias voltage, said fourth MOS transistor (QD4) connected between said first and second dummy cells and a power source and receiving at the gate a fourth bias voltage lower than said third bias voltage; a second load circuit (14B) connected in series between said reference potential node and said first power source for controlling a current flowing through said first and second dummy cells; and a sense amplifier (15) for sensing the data stored in said memory cell in accordance with a potential difference between said reference potential node and said data sensing node.

Claim 22

A semiconductor memory device according to claim 15, characterized in that said first load transistor (QM7B) is a p-channel MOS transistor biased at the gate by a fixed voltage lower than a voltage of said power source, and said second load transistor (QM7A) is a p-channel MOS transistor having the gate connected to said sensing node.

Claim 23

A semiconductor memory device according to claim 16, characterized in that said second load transistor (QM7A) has a larger transconductance than that of said first load transistor.

Claim 24

A semiconductor memory device according to claim 15, characterized in that said first load transistor (QM7B) of said first load circuit is an n-channel MOS transistor whose gate and source are interconnected, and whose threshold voltage is negative.

Claim 25

A semiconductor memory device according to claim 15, characterized in that said second load transistor (QM7A) of said first load circuit is an n-channel MOS transistor biased at the gate by a voltage of said first power source, and having a positive threshold voltage.

Claim 26

A semiconductor memory device according to claim 15, characterized in that said first load transistor (QM7B) of said first load circuit is a p-channel MOS transistor receiving at the gate an internal control signal which is set at a ground potential in response to an external control signal when said memory device is in an active mode, and is set at the potential of said first power source when said memory device is in a stand-by mode.

Claim 27

A semiconductor memory device according to claim 15, characterized in that said second load transistor (QM7A) of said first load circuit is an n-channel MOS transistor receiving at the gate an internal control signal which is set at a potential of said first power source in response to an external control signal when said memory device is in an active mode, and is set at the ground potential when said memory device is in a stand-by mode.

Claim 28

A semiconductor memory device characterized by comprising: row lines (WL1,..., WLm); memory cells (MC11,..., MCmn) selected by said row lines; column lines receiving data from said memory cells; a data sensing node (A); a first bias potential setting circuit (13A) including first and second MOS transistors (QM1, QM4), said first MOS transistor (QM1) being connected between said memory cells and said data sensing node, and receiving at the gate a first bias voltage, said second MOS transistor (QM4) connected between said memory cells and a power source, and receiving at the gate a second bias voltage lower than said first bias voltage; a first load circuit (14A) for controlling a current flowing through said memory cell, said load circuit being connected between said data sensing node and a first power source, said load circuit having a first load transistor (QM7B) for determining a potential of said sensing node by limiting a load current flowing through said load circuit when said memory cell is conductive, and a potential difference between a gate and a source of said first load transistor being independent of the potential of said sensing node, said load circuit having a second load transistor (QM7A) for setting a potential of said sensing node below a potential of said first power source when said memory cell is nonconductive and a potential difference between a gate and a source of said second load transistor being depend on the potential of said sensing node; first dummy cells (DC1,..., DCm) selected by said row lines; a dummy column line (DBL) to which said first dummy cells are connected; a pulse signal generating circuit (18) for gen­erating a pulse signal by detecting a change in an address signal; a second dummy cell (DCm+1) connected to said dummy column line and controlled by a pulse signal from said pulse signal generating circuit; a reference potential node (A); a second bias potential setting circuit (13B) including third and fourth MOS transistors, said third MOS transistor being connected between said first and second dummy cells and said reference potential node and receiving at the gate a third bias voltage, said fourth MOS transistor connected between said first and second dummy cells and a power source and receiving at the gate a fourth bias voltage lower than said third bias voltage; a second load circuit (14B) connected in series between said reference potential node and said first power source for controlling a current flowing through said first and second dummy cells; and a sense amplifier (15) for sensing the data stored in said memory cell in accordance with a potential difference between said reference potential node and said data sensing node.

Claim 29

A semiconductor memory device characterized by comprising: row lines (WL1,..., WLm); memory cells (MC11,..., MCmn) selected by said row lines; column lines receiving data from said memory cells; a data sensing node (A); a first bias potential setting circuit (13A) including first and second MOS transistors (QM1, QM4), said first MOS transistor (QM1) being connected between said memory cells and said data sensing node, and receiving at the gate a first bias voltage, said second MOS transistor (QM4) connected between said memory cells and a power source, and receiving at the gate a second bias voltage lower than said first bias voltage; a first load circuit (14A) for controlling a current flowing through said memory cell, said load circuit being connected between said data sensing node and a first power source, said load circuit having a first load transistor (QM7B) for determining a potential of said sensing node by limiting a load current flowing through said load circuit when said memory cell is conductive, and a potential difference between a gate and a source of said first load transistor being independent of the potential of said sensing node, said load circuit having a second load transistor (QM7A) for setting a potential of said sensing node below a potential of said first power source when said memory cell is nonconductive and a potential difference between a gate and a source of said second load transistor being depend on the potential of said sensing node; first dummy cells (DC1,..., DCm) selected by said row lines; a dummy column line (DBL) to which said first dummy cells are connected; a pulse signal generating circuit (18) for gen­erating a pulse signal by detecting a change in an address signal; a second dummy cell (DCm+1) connected to said dummy column line and controlled by a pulse signal from said pulse signal generating circuit; a reference potential node (A); a second bias potential setting circuit (13B) including third and fourth MOS transistors, said third MOS transistor being connected between said first and second dummy cells and said reference potential node and receiving at the gate a third bias voltage, said fourth MOS transistor connected between said first and second dummy cells and a power source and receiving at the gate a fourth bias voltage lower than said third bias voltage; a second load circuit (14B) connected in series between said reference potential node and said first power source for controlling a current flowing through said first and second dummy cells; and a sense amplifier (15) for sensing the data stored in said memory cell in accordance with a potential difference between said reference potential node and said data sensing node.