EP0347332A2
Expired / Lapsed
EP
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Method of forming semiconductor integrated circuit using master slice approach
Assignee: Fujitsu Ltd
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Filing: 1989-06-16
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Granted: —
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Expires: 2009-06-16
Abstract
Abstract A method of forming a semiconductor integrated circuit using a master slice approach includes the steps of: forming a plurality of transistor regions (TR) with units of a predetermined number in array on a semiconductor chip; forming a plurality of first wirings (LA) extending in parallel at a space therebetween with units of a predetermined length in a discontinuous form so that the first wirings pass through regions corresponding to the transistor regions; forming first contact holes (NA) at predetermined positions so that gate regions (G) and source/drain regions (S/D) of the transistor regions are connected to the first wirings; forming a plurality of second wirings (LB) having same forms as the plurality of first wirings so that the second wirings constitute a mesh-like arrangement in combination with the first wirings; and forming second contact holes (NB) using a pattern mask programmable in accordance with demanded conditions of a given circuit so that the second contact holes connect the second wirings to the first wirings. By changing only the form of the disposition of the second contact holes, it is possible to simplify an entire process to greatly reduce a turnaround time and make an improvement in yield.
Inventors
- 👤 Ryoichi Ohe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 12:47
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; Y; Y10; Y10S; Y10S257/00; Y10S257/909
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
205 words
A method of forming a semiconductor integrated circuit using a master slice approach comprising the steps of: forming a plurality of transistor regions (TR) with units of a predetermined number in an array on a semiconductor chip and then forming a first insulation layer over all said transistor regions; forming a plurality of first wirings (LA) extending in parallel at a space therebetween with units of a predetermined length in a discontinuous form so that said first wirings pass through regions corresponding to said transistor regions; forming first contact holes (NA) at predetermined positions in said first insulation layer so that gate regions (G) and source/drain regions (S/D) of said transistor regions are connected to said first wirings and then forming a second insulation layer over all said first wirings and said first contact holes; forming a plurality of second wirings (LB) having same forms as said plurality of first wirings so that said second wirings constitute a mesh-like arrangement in combination with said first wirings; and forming second contact holes (NB) in said second insulation layer using a pattern mask programmable in accordance with demanded conditions of a given circuit so that said second contact holes connect said second wirings to said first wirings.
Claim 2
Independent Claim
205 words
A method of forming a semiconductor integrated circuit using a master slice approach comprising the steps of: forming a plurality of transistor regions (TR) with units of a predetermined number in an array on a semiconductor chip and then forming a first insulation layer over all said transistor regions; forming a plurality of first wirings (LA) extending in parallel at a space therebetween with units of a predetermined length in a discontinuous form so that said first wirings pass through regions corresponding to said transistor regions; forming first contact holes (NA) at predetermined positions in said first insulation layer so that gate regions (G) and source/drain regions (S/D) of said transistor regions are connected to said first wirings and then forming a second insulation layer over all said first wirings and said first contact holes; forming a plurality of second wirings (LB) having same forms as said plurality of first wirings so that said second wirings constitute a mesh-like arrangement in combination with said first wirings; and forming second contact holes (NB) in said second insulation layer using a pattern mask programmable in accordance with demanded conditions of a given circuit so that said second contact holes connect said second wirings to said first wirings.
Claim 3
Dependent Claim
44 words
A method as set forth in claim 1, wherein a pattern of said first and second wirings formed on regions corresponding to said transistor regions is the same as that formed on regions corresponding to a field region (F) other than said transistor regions.
Claim 4
Dependent Claim
33 words
A method as set forth in claim 2, wherein the number of said first wirings extending in parallel at a space therebetween is three, and that of said second wirings is also three.
Claim 5
Dependent Claim
43 words
A method as set forth in claim 3, wherein the step of forming said plurality of first wirings includes a step of forming wirings for power supply lines so that they extend in a continuous form along a first direction of said chip.
Claim 6
Dependent Claim
49 words
A method as set forth in claim 4, wherein the step of forming said plurality of second wirings includes a step of forming wirings for power supply lines so that they extend in a continuous form along said first direction and a second direction perpendicular to said first direction.
Claim 7
Dependent Claim
33 words
A method as set forth in claim 5, wherein said wirings for power supply lines formed in the step of forming said first wirings extend in a continuous form along said second direction.
Claim 8
Independent Claim
202 words
A method of forming a semiconductor integrated circuit using a master slice approach comprising the steps of: forming a plurality of transistor regions (TR) with units of a predetermined number in array on a semiconductor chip and then forming a first insulation layer over all said transistor regions; forming a plurality of first wirings (LA) extending in parallel at a space therebetween with units of a predetermined length in a discontinuous form so that said first wirings pass through regions corresponding to said transistor regions; forming first contact holes (NA) at predetermined positions in said first insulation layer and then forming a second insulation layer all over said first wirings and said first contact holes; forming a plurality of second wirings (LB) having same forms as said plurality of first wirings so that said second wirings constitute a mesh-like arrangement in combination with said first wirings; and forming second contact holes (NB) in said second insulation layer using a pattern mask programmable in accordance with demanded conditions of a given circuit so that said second contact holes connect said second wirings via said first wirings and said first contact holes to gate regions (G) and source/drain regions (S/D) of said transistor regions.
Claim 9
Independent Claim
202 words
A method of forming a semiconductor integrated circuit using a master slice approach comprising the steps of: forming a plurality of transistor regions (TR) with units of a predetermined number in array on a semiconductor chip and then forming a first insulation layer over all said transistor regions; forming a plurality of first wirings (LA) extending in parallel at a space therebetween with units of a predetermined length in a discontinuous form so that said first wirings pass through regions corresponding to said transistor regions; forming first contact holes (NA) at predetermined positions in said first insulation layer and then forming a second insulation layer all over said first wirings and said first contact holes; forming a plurality of second wirings (LB) having same forms as said plurality of first wirings so that said second wirings constitute a mesh-like arrangement in combination with said first wirings; and forming second contact holes (NB) in said second insulation layer using a pattern mask programmable in accordance with demanded conditions of a given circuit so that said second contact holes connect said second wirings via said first wirings and said first contact holes to gate regions (G) and source/drain regions (S/D) of said transistor regions.
References Cited (Backward Citations)
No citation records indexed.
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