EP0347148A2
Expired / Lapsed
EP
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Semi-conductor non-volatile memory
Assignee: Seiko Instruments Inc
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Filing: 1989-06-12
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Granted: —
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Expires: 2009-06-12
Abstract
Abstract A semi-conductor non-volatile memory device comprises a semi-conductor substrate (1), an electrically erasable programmable memory cell and a peripheral circuit. The memory cell has a gate oxide film (4) disposed on the substrate, a floating gate electrode (5) formed on the gate oxide film, and a control gate electrode (7) formed in the substrate under the gate oxide film and separated from the floating gate electrode through the gate oxide film for controlling the al level of the floating gate electrode to effect writing and erasing of the memory cell. The peripheral circuit includes a transistor (12, 13, 15) having another gate oxide film (14) disposed on the substrate and formed concurrently with the gate oxide film of the memory cell.
Inventors
- 👤 Kazutoshi C/O Seiko Instruments Inc. Ishii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 21:16
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
93 words
A semi-conductor non-volatile memory device comprising a semi-conductor substrate (1), and an electrically erasable programmable memory cell having a gate oxide film (4) disposed on the substrate, a floating gate electrode (5) formed on the gate oxide film, and a control gate electrode (7) for controlling the potential level of the floating gate electrode to effect writing and erasing of the memory cell, characterised in that the control gate electrode is formed in the substrate under the gate oxide film and is separated from the floating gate electrode through the gate oxide film.
Claim 2
Dependent Claim
93 words
A semi-conductor non-volatile memory device comprising a semi-conductor substrate (1), and an electrically erasable programmable memory cell having a gate oxide film (4) disposed on the substrate, a floating gate electrode (5) formed on the gate oxide film, and a control gate electrode (7) for controlling the potential level of the floating gate electrode to effect writing and erasing of the memory cell, characterised in that the control gate electrode is formed in the substrate under the gate oxide film and is separated from the floating gate electrode through the gate oxide film.
Claim 3
Dependent Claim
41 words
A memory device according to claim 1 characterised by a peripheral circuit including a transistor (12, 13, 15) having a further gate oxide film (14) disposed on the substrate and formed concurrently with the gate oxide film of the memory cell.
Claim 4
Dependent Claim
43 words
A memory device according to claim 2 characterised in that the transistor has a transistor gate electrode (15) formed on the further gate oxide film concurrently with the formation of the floating gate electrode on the gate oxide film of the memory cell.
Claim 5
Independent Claim
103 words
A method of forming a semi-conductor non-volatile memory device comprising the steps of forming a gate oxide film (4) on a semi-conductor substrate (1), forming a floating gate electrode (5) on the gate oxide film, and providing a control gate electrode (7) for controlling the potential level of the floating gate electrode to effect writing and erasing of the memory cell, characterised in that the control gate electrode is formed in the substrate prior to the formation of the gate oxide film on the substrate so as to separate the control gate electrode from the floating gate electrode through the gate oxide film.
Claim 6
Independent Claim
103 words
A method of forming a semi-conductor non-volatile memory device comprising the steps of forming a gate oxide film (4) on a semi-conductor substrate (1), forming a floating gate electrode (5) on the gate oxide film, and providing a control gate electrode (7) for controlling the potential level of the floating gate electrode to effect writing and erasing of the memory cell, characterised in that the control gate electrode is formed in the substrate prior to the formation of the gate oxide film on the substrate so as to separate the control gate electrode from the floating gate electrode through the gate oxide film.
Claim 7
Dependent Claim
38 words
A method according to claim 4 characterised by forming a peripheral circuit including a transistor (12, 13, 15), the transistor including a further gate oxide film (14) formed concurrently with the gate oxide film of the memory cell.
Claim 8
Dependent Claim
41 words
A method according to claim 5 characterised by forming a transistor gate electrode (15) of the transistor on the further gate oxide film concurrently with the formation of the floating gate electrode on the gate oxide film of the memory cell.
References Cited (Backward Citations)
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