Bus stealing method for concurrent CPU and I/O processing

Claim 2

A computer system with a CPU, a main memory, a support controller, a direct memory access controller, one or several I/O devices and a common bus, wherein a bus steal logic is provided, which, when during I/O data transfer to said main memory said CPU requires access to said main memory, sends a first signal to said direct memory access controller which causes direct memory access controller to halt said I/O data transfer and a second signal to said support controller which gives said CPU access to said main memory.

Claim 3

A computer system as defined in claim 1 wherein a cache memory is attached to said CPU, said support controller is a cache controller and said common bus consists of a CPU-bus, memory bus and 1/O-bus.

Claim 4

A computer system as defined in claim 1 wherein said bus steal logic comprises two inputs and four outputs.

Claim 5

A computer system as defined in claim 1, wherein a logical device is provided which comprises: a request input for receiving first request signals from said I/O devices, a steal input for receiving steal signals from said bus steal logic, a request output for sending second request signals to said direct memory access controller and wherein through the logical combination of said steal signals said first request signals said second request signal is transmitted to said direct memory access controller if one of said I/O devices requires access and said CPU has no access to said main memory.

Claim 6

A computer system as described in claim 4, comprising: a DMA request input port to receive said second request signals; a hold output port to send hold signals to said bus steal logic when said second request signals are received; a hold acknowledge input port to receive hold acknowledge signals send by said bus steal logic.

Claim 7

A computer system as described in claim 5, which sends said steal signal to said logical device when said support controller requires access for said CPU to said main memory and connects said I/O bus with said memory bus by control signal, comprising: a hold request input port 8 to receive said holdsignals from said direct memory access controller; a hold acknowledge output port B to send said hold acknowledge signals to said direct memory access controller; a hold request input port A to receive hold signals from said support controller; a hold acknowledge output port A to send hold acknowledge signals to said support controller; a control output port to send a control signal to a device which connects said memory bus to said I/O-bus; a steal output port to send said steal signals to said logical device;

Claim 8

A computer system as described in claim 6, which sends a hold signal to said hold request input port A of said bus steal logic if said CPU requires access to said main memory and connects said CPU bus with said memory bus by control signal, comprising: a hold output port to send said hold signals to said bus steal logic; a hold acknowledge input port to receive said hold acknowledge signals from said bus steal logic; a ready output port to send ready signal to said CPU; a control output port to send a control signal to a device which connects said memory bus with said CPU-bus.