EP0346629A2
Expired / Lapsed
EP
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Memory card architecture and interface
Assignee: International Business Machines Corp
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Filing: 1989-05-17
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Granted: —
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Expires: 2009-05-17
Abstract
Abstract A "smart" memory card architecture and interface provides significantly increased performance, in part, by using fast access dynamic random access memory (DRAM) technologies which allows up to 8-byte data transfers from the memory card every 27ns after the initial access. The 27ns transfer rate includes the time required for error correction code (ECC), parity generation, and other reliability functions. Only two complementary metal oxide semiconductor (CMOS) integrated circuit (IC) logic chips or modules provide all the function required. The simplicity and flexibility afforded by the "smart" memory card approach provides a means to allow one card interface to be used with a broad range of hardware technologies and in different systems. The architecture of the memory card provides a full range of direct and partial store operations in a manner transparent to the system.
Inventors
- 👤 David L. Arlington
- 👤 Jacqueline Morris Cole
- 👤 Bruce G. Hazelzet
- 👤 David J. Krolak
- 👤 Hehching Harry Li
- 👤 Bharat J. Oza
- 👤 A. Frank Weaver
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 02:12
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G06F11/106; G06F11/1012; G06F11/1028; G06F11/1056
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
200 words
A memory card of the type including a memory array (40) communicating with a system bus via on-card logic, said on-card logic comprising: first latch means (51) connected to receive data from said memory array (40) for temporarily storing said data; error correction code means (55) connected to receive data from said first latch means (51) for performing error detection and correction on said data; second latch means (57) connected to receive data from said error correction code means (55) for temporarily storing said data; and data output select means (59) connected to receive data from said error correction code means (55) and said second latch means (57) for selectively transmitting data to said system bus; wherein said first latch means (51), said error correction code means (55) and said second latch means (57) each comprise odd (b) and even (a) parts, said data output select means (59) being connected to receive data from both odd and even parts of said error correction code means (55a, 55b) and said second latch means (57a, 57b), said on-card logic further comprising control means for controlling said data output select means (59) to interleave data from said odd (b) and even (a) parts.
Claim 2
Dependent Claim
200 words
A memory card of the type including a memory array (40) communicating with a system bus via on-card logic, said on-card logic comprising: first latch means (51) connected to receive data from said memory array (40) for temporarily storing said data; error correction code means (55) connected to receive data from said first latch means (51) for performing error detection and correction on said data; second latch means (57) connected to receive data from said error correction code means (55) for temporarily storing said data; and data output select means (59) connected to receive data from said error correction code means (55) and said second latch means (57) for selectively transmitting data to said system bus; wherein said first latch means (51), said error correction code means (55) and said second latch means (57) each comprise odd (b) and even (a) parts, said data output select means (59) being connected to receive data from both odd and even parts of said error correction code means (55a, 55b) and said second latch means (57a, 57b), said on-card logic further comprising control means for controlling said data output select means (59) to interleave data from said odd (b) and even (a) parts.
Claim 3
Dependent Claim
69 words
A memory card as recited in claim 1 wherein said memory array (40) includes an internal memory bus (41, 42) which is n-bytes wide and said system bus is n/2-bytes wide, said data output select means (59) interleaves n-byte wide data from said error correcting code means (55) and said second latch means (57) to from contiguous n/2-byte data on said system bus in response to said control means.
Claim 4
Dependent Claim
89 words
A memory card as recited in claim 1 or 2 wherein said data output select means (59) comprises: slow multiplexer means (73) connected to receive data from said odd and even parts of said second latch means (57) for selectively passing data therefrom in response to said control means; and fast multiplexer means (74) connected to receive data from said odd an even parts of said error correction code means (55) and from said slow multiplexer means (73) for selectively passing data therefrom in response to said control means.
Claim 5
Dependent Claim
91 words
A memory card as recited in claim 3 further comprising: internal data loop register means (54) connected to receive data from said error correcting code means (55) for temporarily storing said data; and flow select logic means (52) connected to receive data from said internal loop register means (54) and said first latch means (51) for selectively supplying data therefrom to said error correcting code means (55), said internal data loop register means (54) and said flow select logic means (52) providing an optimized error correction code path for said data.
Claim 6
Dependent Claim
64 words
A memory card as recited in claim 4 further comprising memory store buffer means (53) connected to receive data from said system bus for temporarily storing said data, said flow select logic means (52) also being connected to receive data from said memory store buffer means (53), said memory store buffer means (53) buffering data during a read-modify-write operation to said memory array (40).
Claim 7
Dependent Claim
117 words
A memory card as recited in at least one of claims 1 to 5 wherein said control means comprises: array control means (63) for activating said memory array (40) for fetch and store operations; data flow control means (65) for performing diagnostic and self test operations; supervisor control means (64) for controlling said array control means (63) and said data flow control means (65); control bus means (66) for interconnecting said array control means (63), said data flow control means (65) and said supervisor control means (64); and clock means (67) connected to each of array control means (63), said data flow control means (65) and said supervisor control means (64) for supplying synchronizing clock pulses thereto.
Claim 8
Dependent Claim
92 words
A memory card as recited in claim 6 wherein said array control means (64) includes: refresh counter means (69) for counting refresh cycles of said memory array (40); scrub counter means (70) for counting soft error scrub operations performed on said memory array (40); and wherein said control means further compares counts in said refresh (69) and scrub (70) counter means for controlling back-to-back zero byte read-modify-write operations to said memory array (40) to effect said soft error scrub operations, said soft error scrub operations being performed transparently during a refresh operation.
Claim 9
Dependent Claim
43 words
A memory card as recited in claim 6 or 7 wherein said data flow control means (65) includes special function register means (72) for modifying how commands are executed in the data flow and how data flow paths are configured for any operation.
Claim 10
Dependent Claim
52 words
A memory card as recited in at least one of claims 6 to 8 wherein said supervisor control means (64) includes program register means (71) for personalizing operations of the card based on system input as determined by what kind of card types are plugged in and what the system configuration is.
References Cited (Backward Citations)
No citation records indexed.
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