EP0345435A2
Expired / Lapsed
EP
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Semiconductor device with a high breakdown voltage and method for its manufacture
Assignee: Toshiba Corp
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Filing: 1989-04-07
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Granted: —
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Expires: 2009-04-07
Abstract
Abstract Phosphorus is doped into one of the major surfaces of an n-type silicon semiconductor substrate (10), and boron is doped into the other major surface. Thereafter, the structure is diffused into the surface regions of the substrate at a high temperature and for a long time, so that an n-buffer layer (11) is formed in the first major surface, and a p-base layer (12) is formed in the second major surface. Impurity of n-type is diffused into the p-base layer (12), to form an n-emitter layer (13). Impurity of p-type is diffused into the n-buffer layer (11), to selectively form p-emitter layer (13). Further, n-type impurity is diffused into the n-buffer layer (11), to form n-type anode short layer (15).
Inventors
- 👤 Mitsuhiko C/O Patent Division Kitagawa
- 👤 Yoshio C/O Patent Division Yokota
- 👤 Kazuo C/O Patent Division Watanuki
- 👤 Yoshinari C/O Patent Division Uetake
- 👤 Kazunobu C/O Patent Division Nishitani
- 👤 Tsuneo C/O Patent Division Ogura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 15:02
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/01; H10D18/60; H10D62/00; H10D62/10; H10D62/117; H10D62/13; H10D62/141; H10D62/142; H10D62/60; H10D8/00; H10D8/50; H10W; H10W72/00; H10W76/00; H10W76/10; H10W76/12; H10W76/13; H10W76/138
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
83 words
A semiconductor device of high withstand voltage comprising: an n-type first semiconductor layer of high sheet resistance (10, 31, 61, 81); a p-type second semiconductor layer (12, 32, 62, 83) doped with boron as an impurity, said second semiconductor layer being formed in a first major surface of said first semiconductor layer; an n-type third semiconductor layer (11, 34, 64, 82) doped with phosphorus as an impurity, said second semiconductor layer being formed in a second major surface of said first semiconductor layer.
Claim 2
Dependent Claim
83 words
A semiconductor device of high withstand voltage comprising: an n-type first semiconductor layer of high sheet resistance (10, 31, 61, 81); a p-type second semiconductor layer (12, 32, 62, 83) doped with boron as an impurity, said second semiconductor layer being formed in a first major surface of said first semiconductor layer; an n-type third semiconductor layer (11, 34, 64, 82) doped with phosphorus as an impurity, said second semiconductor layer being formed in a second major surface of said first semiconductor layer.
Claim 3
Dependent Claim
57 words
The semiconductor device according to claim 1, characterized in that a sheet resistance and a width of said first semiconductor layer are selected so as to satisfy the following relation ρn/Wn ≧ 1 × 10⁴ where ρn : sheet resistance (ohm·cm) of said first semiconductor layer (10, 31, 61, 81), wn : width (cm) of the same.
Claim 4
Dependent Claim
36 words
The semiconductor device according to claim 1, characterized in that an n-type fourth semiconductor layer (15, 37, 84) of high impurity concentration is further formed in the surface of said third semiconductor layer (11, 34, 82).
Claim 5
Independent Claim
108 words
A method of manufacturing semiconductor devices of high withstand voltage comprising: a first step of introducing an impurity of boron into a first major surface of an n-type first semiconductor layer (10) of high sheet resistance and an impurity of phosphorus into a second major surface of said first semiconductor layer; and a second step of forming a second semiconductor layer (12) of p-type in said first major surface of said first semiconductor layer (10) and a third semiconductor layer (11) of n-type in said second major surface of said first semiconductor layer by diffusing said impurities into said first and second surfaces of said first semiconductor layer.
Claim 6
Independent Claim
108 words
A method of manufacturing semiconductor devices of high withstand voltage comprising: a first step of introducing an impurity of boron into a first major surface of an n-type first semiconductor layer (10) of high sheet resistance and an impurity of phosphorus into a second major surface of said first semiconductor layer; and a second step of forming a second semiconductor layer (12) of p-type in said first major surface of said first semiconductor layer (10) and a third semiconductor layer (11) of n-type in said second major surface of said first semiconductor layer by diffusing said impurities into said first and second surfaces of said first semiconductor layer.
Claim 7
Dependent Claim
48 words
The method according to claim 4, characterized in that said first step includes a third step to introduce phosphorus into a first major surface of said first semiconductor layer (10), and a 4th step to introduce boron into a second major surface of said first semiconductor layer (10).
Claim 8
Dependent Claim
21 words
The method according to claim 5, characterized in that said third and fourth steps are performed by an ion implanting method.
Claim 9
Dependent Claim
57 words
The method according to claim 4, characterized in that said second step includes a 5th step of simultaneously pre-drive-in diffusing both of said impurities by heating them at a predetermined temperature, and a 6th step of simultaneously diffusing both said impurities for a much longer time and at a higher temperature than those in said pre-drive-in diffusion.
Claim 10
Independent Claim
173 words
A method of manufacturing semiconductor devices of high withstand voltage comprising: a first step of introducing an impurity of boron into a first major surface of an n-type base layer (10) of high sheet resistance and an impurity of phosphorus into a second major surface of said base layer; a second step of simultaneously forming a p-type base layer (12) in said first major surface of said base layer (10) and an n-type buffer layer (11) in second major surface of said base layer (10) by diffusing said impurities into said first and second major surfaces of said base layer (10); a third step of introducing different types of impurities of different conductivity types into said p-type base layer (12) and said n-type buffer layer (11); and a fourth step of simultaneously forming an n-type emitter layer (13) in said p-type base layer (12), and a p-type emitter layer (14) and an n-type anode short layer (15) in said n-type buffer layer (11) by diffusing said impurities as introduced in said third step.
Claim 11
Independent Claim
173 words
A method of manufacturing semiconductor devices of high withstand voltage comprising: a first step of introducing an impurity of boron into a first major surface of an n-type base layer (10) of high sheet resistance and an impurity of phosphorus into a second major surface of said base layer; a second step of simultaneously forming a p-type base layer (12) in said first major surface of said base layer (10) and an n-type buffer layer (11) in second major surface of said base layer (10) by diffusing said impurities into said first and second major surfaces of said base layer (10); a third step of introducing different types of impurities of different conductivity types into said p-type base layer (12) and said n-type buffer layer (11); and a fourth step of simultaneously forming an n-type emitter layer (13) in said p-type base layer (12), and a p-type emitter layer (14) and an n-type anode short layer (15) in said n-type buffer layer (11) by diffusing said impurities as introduced in said third step.
Claim 12
Dependent Claim
48 words
The method according to claim 8, characterized in that said first step includes a 5th step to introduce phosphorus into a first major surface of said first semiconductor layer (10), and a 6th step to introduce boron into a second major surface of said first semiconductor layer (10).
Claim 13
Dependent Claim
21 words
The method according to claim 9, characterized in that said 5th and 6th steps are performed by an ion implanting method.
Claim 14
Dependent Claim
57 words
The method according to claim 8, characterized in that said second step includes a 7th step of simultaneously pre-drive-in diffusing both of said impurities by heating them at a predetermined temperature, and an 8th step of simultaneously diffusing both said impurities for a much longer time and at a higher temperature than those in said pre-drive-in diffusion.
Claim 15
Dependent Claim
75 words
The method according to claim 8, characterized in that said third step further includes a 9th of introducing, by using predetermined masks (24, 27), an n-type impurity into the entire surface of said p-type base layer (12), and selectively introducing a p-type impurity into a part of the surface of said n-type buffer layer (11), and a 10th steps of selectively introducing an n-type impurity into the surface portion of said n-type buffer layer (11).
Claim 16
Dependent Claim
22 words
The method according to claim 8, characterized in that said anode short layer (15) is shallower than said p-type emitter layer (14).
Claim 17
Independent Claim
179 words
A method of manufacturing semiconductor devices of high withstand viltage comprising: a first step of introducing an impurity of boron into a first major surface of an n-type base layer (10) of high sheet resistance and an impurity of phosphorus into a second major surface of said base layer; a second step of simultaneously forming a p-type base layer (12) in said first major surface of said base layer (10) and an n-type buffer layer (11) in second major surface of said base layer (10) by diffusing said impurities into said first and second major surfaces of said base layer (10); a third step of selectively introducing a p-type impurity into said n-type buffer layer (11), and diffusing the impurity to form a p-type emitter layer (14); and a fourth step of forming an n-type emitter layer (13) in said p-type base layer (12), and an n-type anode short layer (15) in said n-type buffer layer (11) by selectively introducing a p-type impurity into said p-type base layer (12) and said n-type buffer layer (11) and diffusing them thereinto.
Claim 18
Independent Claim
179 words
A method of manufacturing semiconductor devices of high withstand viltage comprising: a first step of introducing an impurity of boron into a first major surface of an n-type base layer (10) of high sheet resistance and an impurity of phosphorus into a second major surface of said base layer; a second step of simultaneously forming a p-type base layer (12) in said first major surface of said base layer (10) and an n-type buffer layer (11) in second major surface of said base layer (10) by diffusing said impurities into said first and second major surfaces of said base layer (10); a third step of selectively introducing a p-type impurity into said n-type buffer layer (11), and diffusing the impurity to form a p-type emitter layer (14); and a fourth step of forming an n-type emitter layer (13) in said p-type base layer (12), and an n-type anode short layer (15) in said n-type buffer layer (11) by selectively introducing a p-type impurity into said p-type base layer (12) and said n-type buffer layer (11) and diffusing them thereinto.
Claim 19
Dependent Claim
48 words
The method according to claim 14, characterized in that said first step includes a 5th step to introduce phosphorus into a first major surface of said first semiconductor layer (10), and a 6th step to introduce boron into a second major surface of said first semiconductor layer (10).
Claim 20
Dependent Claim
21 words
The method according to claim 15, characterized in that said 5th and 6th steps are performed by an ion implanting method.
Claim 21
Dependent Claim
57 words
The method according to claim 14, characterized in that said second step includes a 7th step of simultaneously pre-drive-in diffusing both of said impurities by heating them at a predetermined temperature, and an 8th step of simultaneously diffusing both said impurities for a much longer time and at a higher temperature than those in said pre-drive-in diffusion.
Claim 22
Dependent Claim
22 words
The method according to claim 14, characterized in that said p-type emitter layer (14) is shallower than said anode short layer (15).
References Cited (Backward Citations)
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