EP0344632A2
Expired / Lapsed
EP
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Semiconductor memory device having pseudo row decoder
Assignee: Fujitsu VLSI Ltd
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Filing: 1989-05-26
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Granted: —
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Expires: 2009-05-26
Abstract
Abstract A semiconductor memory device includes: a memory cell array (1) including a plurality of word lines (WL); a row pre-decoding unit (2) responsive to a row address signal, outputting a plurality of row pre-decode signals with units of a group having signals of a number corresponding to a combination of each logic level of a predetermined plurality of bits of the row address signal; a row pre-decode wiring (3, 3L, 3R) for transmitting the plurality of row pre-decode signals; a row main decoder (4) responsive to one signal in each group of the plurality of row pre-decode signals, carrying out a main decoding for selecting one of the plurality of word lines; a pseudo row decoder (5) having substantially same electrical characteristics as said row main decoder, carrying out a simulation of said main decoding in response to said plurality of row pre-decode signals output on said row pre-decode wiring; and a word line driver (6) for driving a word line selected by the row main decoder to a predetermined level. An operation of the word line driver is started in response to an activation of the pseudo row decoder, thereby excluding a possibility of an erroneous selection of a word line and preventing an unnecessary prolongation of an access time.
Inventors
- 👤 Yukinori Kodama
- 👤 Takaaki Furuyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 23:47
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C8/00; G11C8/08; G11C8/10; G11C8/12; G11C8/18
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
206 words
A semiconductor memory device comprising: a memory cell array (1) including a plurality of word lines (WL); a row pre-decoding means (2) responsive to a row address signal (RA, A₀ - A₆), outputting a plurality of row pre-decode signals (φ₀₀ - φ₀₃; φ₁₀ - φ₁₃; φ₂₀ - φ₂₃) with units of a group having signals of a number corresponding to a combination of each logic level of a predetermined plurality of bits of said row address signal; a row pre-decode wiring (3, 3L, 3R) for transmitting said plurality of row pre-decode signals; and a row main decoder (4) responsive to one signal in each group of said plurality of row pre-decode signals, carrying out a main decoding for selecting one of said plurality of word lines, characterized by: a pseudo row decoder (5) having substantially same electrical characteristics as said row main decoder, carrying out a simulation of said main decoding in response to said plurality of row pre-decode signals output on said row pre-decode wiring; and a word line driver (6) for driving a word line selected by said row main decoder to a predetermined level, an operation of said word line driver being started in response to an activation of said pseudo row decoder.
Claim 2
Dependent Claim
206 words
A semiconductor memory device comprising: a memory cell array (1) including a plurality of word lines (WL); a row pre-decoding means (2) responsive to a row address signal (RA, A₀ - A₆), outputting a plurality of row pre-decode signals (φ₀₀ - φ₀₃; φ₁₀ - φ₁₃; φ₂₀ - φ₂₃) with units of a group having signals of a number corresponding to a combination of each logic level of a predetermined plurality of bits of said row address signal; a row pre-decode wiring (3, 3L, 3R) for transmitting said plurality of row pre-decode signals; and a row main decoder (4) responsive to one signal in each group of said plurality of row pre-decode signals, carrying out a main decoding for selecting one of said plurality of word lines, characterized by: a pseudo row decoder (5) having substantially same electrical characteristics as said row main decoder, carrying out a simulation of said main decoding in response to said plurality of row pre-decode signals output on said row pre-decode wiring; and a word line driver (6) for driving a word line selected by said row main decoder to a predetermined level, an operation of said word line driver being started in response to an activation of said pseudo row decoder.
Claim 3
Dependent Claim
59 words
A device as set forth in claim 1, wherein said row pre-decoding means (2) comprises a plurality of row pre-decoders (2A, 2B, 2C; 2D, 2E, 2F) and said pseudo row decoder (5) carries out said simulation in response to the output of a row pre-decoder (2C, 2F) located at the farthest position therefrom among said plurality of row pre-decoders.
Claim 4
Dependent Claim
86 words
A device as set forth in claim 2, comprising said memory cell array (1) in a plurality of numbers, wherein said plurality of memory cell arrays are divided into two regions and said plurality of row pre-decoders are provided between said two regions and divided into a first half (2A, 2B, 2C) allocated for one of said two regions and a second half (2D, 2E, 2F) allocated for another thereof, one of said first and second halves being selected in response to a select signal (A₆).
Claim 5
Dependent Claim
62 words
A device as set forth in claim 3, wherein each of said plurality of row pre-decoders comprises a plurality of transistors (23, 24) connected in series and responding to each of said predetermined plurality of bits of the row address signal, and outputs said group of row pre-decode signals in accordance with the ON/OFF operation of said transistors in a selection state.
Claim 6
Dependent Claim
76 words
A device as set forth in claim 2, wherein said row main decoder (4) comprises a plurality of transistors (43 - 45) connected in series and responding to one signal (φ₀₀ , φ₁₁ , φ₂₂) in each group of said plurality of row pre-decode signals output on said row pre-decode wiring, respectively, and outputs a first signal (V₂) indicating a result of said main decoding in accordance with the ON/OFF operation of said plurality of transistors.
Claim 7
Dependent Claim
72 words
A device as set forth in claim 5, wherein said row main decoder (4) further comprises a first transistor (47) connected between an output end of said word line driver and one of said plurality of word lines and a second transistor (46) responding to a second signal (φ₂) having an enough level to turn ON said second transistor and transferring said first signal (V₂) to a gate of said first transistor.
Claim 8
Dependent Claim
51 words
A device as set forth in claim 6, wherein said first transistor (47) drives a corresponding word line to said predetermined level based on an output signal (φ₃) of said word line driver when said first signal (V₁) applied to the gate thereof represents a selection of the corresponding word line.
Claim 9
Dependent Claim
69 words
A device as set forth in claim 7, wherein said pseudo row decoder (5) comprises a plurality of transistors (53A - 53D) connected in parallel and responding to each signal (φ₂₀ - φ₂₃) among said group arriving last at said pseudo row decoder, respectively, and outputs an activation signal for said word line driver in response to the ON operation of at least one of said plurality of transistors.
Claim 10
Dependent Claim
50 words
A device as set forth in claim 8, wherein said pseudo row decoder (5) further comprises a transistor (56) responding to said second signal (φ₂) and transferring said activation signal to said word line driver with the same timing as that in the transfer operation of said second transistor (46).
Claim 11
Dependent Claim
35 words
A device as set forth in claim 9, wherein said word line driver (6) outputs said output signal (φ₃) for driving a selected word line to said predetermined level on receiving said activation signal (φ₅).
Claim 12
Dependent Claim
35 words
A device as set forth in claim 1, wherein said substantially same electrical characteristics of the pseudo row decoder are defined by the same number of logic stages as those in said row main decoder.
Claim 13
Dependent Claim
45 words
A device as set forth in claim 1, wherein said pseudo row decoder carries out said simulation in response to a group (φ₂₀ - φ₂₃) arriving last at said pseudo row decoder among said plurality of row pre-decode signals output on said row pre-decode wiring.
References Cited (Backward Citations)
No citation records indexed.
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