EP0344467B1
Expired / Lapsed
EP
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Quadrature receiver
Assignee: Alcatel Lucent Deutschland AG
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Filing: 1989-04-28
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Granted: 1992-08-19
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Expires: 2009-04-28
Abstract
Abstract A quadrature receiver is disclosed which contains two mixers (M1, M3) in an in-phase receiving path and two mixers (M2, M4) in a quadrature receiving path for converting a received signal to a low IF. Each of the mixers is fed with an oscillator signal (O1 through O4), with the oscillator signal fed to one mixer of the respective receiving path having alternately the same or opposite phase from that of the oscillator signal fed to the other mixer of the same receiving path. In each receiving path, the mixers are followed by a circuit (P', P'') which delivers an in-phase signal and a quadrature signal, respectively. These circuits compensate for the DC offset caused by the mixers.
Inventors
- 👤 Dietrich Dr. Rother
- 👤 Bernd Dr. Ripka
- 👤 Rainer Berger
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 22:25
CPC Classifications
H; H03; H03D; H03D7/00; H03D7/16; H03D7/165; H03D1/00; H03D1/22; H03B; H03B27/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
193 words
Receiver comprising an oscillator and at least a first mixer (M1) and a second mixer (M2) which mix a received signal with a first oscillator signal (O1) and a second oscillator signal (O2), respectively, which differ in phase by 90°, characterized in that the receiver further includes a third mixer (M3) and a fourth mixer (M4) which mix the received signal with a third oscillator signal (O3) and a fourth oscillator signal (O4), respectively, with the third oscillator signal being alternately in phase with and in phase opposition to the first oscillator signal, and the fourth oscillator signal being alternately in phase with and in phase opposition to the second oscillator signal, that the receiver contains a first circuit (P′, D′, W′) which has two inputs the first of which follows the first mixer and the second of which follows the third mixer, and which provides an in-phase signal at its output, and that the receiver contains a second circuit (P˝, D˝, W˝) which has two inputs the first of which follows the second mixer and the second of which follows the fourth mixer, and which provides a quadrature signal at its output.
Claim 2
Dependent Claim
193 words
Receiver comprising an oscillator and at least a first mixer (M1) and a second mixer (M2) which mix a received signal with a first oscillator signal (O1) and a second oscillator signal (O2), respectively, which differ in phase by 90°, characterized in that the receiver further includes a third mixer (M3) and a fourth mixer (M4) which mix the received signal with a third oscillator signal (O3) and a fourth oscillator signal (O4), respectively, with the third oscillator signal being alternately in phase with and in phase opposition to the first oscillator signal, and the fourth oscillator signal being alternately in phase with and in phase opposition to the second oscillator signal, that the receiver contains a first circuit (P′, D′, W′) which has two inputs the first of which follows the first mixer and the second of which follows the third mixer, and which provides an in-phase signal at its output, and that the receiver contains a second circuit (P˝, D˝, W˝) which has two inputs the first of which follows the second mixer and the second of which follows the fourth mixer, and which provides a quadrature signal at its output.
Claim 3
Dependent Claim
51 words
A receiver as claimed in claim 1, characterized in that the first circuit (P′, D′, W′) and the second circuit (P˝, D˝, W˝) are identical in construction, and that a low-pass filter (TP1-TP4) is connected between each of the mixers (M1-M4) and the associated circuits (P′, D′, W′, P˝, D˝, W˝).
Claim 4
Dependent Claim
23 words
A receiver as claimed in claim 1 or 2, characterized in that the mixers (M1-M4) convert the input signal to a zero IF.
Claim 5
Dependent Claim
145 words
A receiver as claimed in claim 1, 2, or 3, characterized in that each circuit (P′, P˝) contains an adder (A′), two subtracters (S1, S2), a changeover switch (U˝), and an integrator (I′), that the adder (A′) adds the signals applied to the first and second inputs, that the first subtracter (S1) subtracts the signal applied to the second input from the signal applied to the first input, that either the output of the adder (A′) or that of the first subtracter (S1) is applied via the changeover switch (U˝) to the integrator (I′), with the changeover switch (U˝) being operated synchronously with the phase reversals of the phase-alternating oscillator signal, and that the output signal of the integrator (I′) is subtracted by the second subtracter (S2) from the signal applied to the first input to obtain the output signal of the circuit (P′, P˝).
Claim 6
Dependent Claim
50 words
A receiver as claimed in claim 4, characterized in that each circuit (P′, P˝) contains a controller (R) following the integrator (I′), and that instead of the signal applied at the,first input, the output of the second subtractor (S2) is applied to the adder (A′) and the first subtractor (S1).
Claim 7
Dependent Claim
91 words
A receiver as claimed in claim 1, 2, or 3, characterized in that in zero-IF receivers, in order to compensate for the DC offset in the signals provided by the mixers, the circuit (D′, D˝) has a subtracter (S) at each of its two inputs which subtracters are followed by an arithmetic unit (RR) for computing compensation signals which are applied to the inverting inputs of the subtracters (S), and that the output signal of the circuit (D′, D˝) is obtainable from the output of the subtracter behind the first input.
Claim 8
Dependent Claim
30 words
A receiver as claimed in claim 6, characterized in that the arithmetic unit (RR) is preceded by at least one A/D converter (AD) and followed by two D/A converters (DA).
Claim 9
Dependent Claim
197 words
A receiver as claimed in claim 2, characterized in that the received signal is converted by the oscillator signals (O1-O4) to a low IF different from zero, that each circuit (W′, W˝) has a further mixer (M˝) at its second input and a subtracter (S) followed by another mixer (M′) at its first input which convert their input signals to a high IF by means of two auxiliary signals, with the auxiliary signal for the further mixer (M˝) being alternately in phase with and in phase opposition to the other auxiliary signal, and the phases of the auxiliary signals in the two circuits (W′, W˝) separated by 90°, that the other mixer (M′) and the further mixer (M˝) are followed by an adder (A) having its output connected to an additional mixer (M) followed by an integrator (I) whose output is fed through a controller (R) to the inverting input of the subtracter (S), that the additional mixer (M) converts the signal from the adder (A) to the low IF by means of the other auxiliary signal, and that the output signal of the circuit (W′, W˝) is obtainable from the output of the other mixer (M′).
References Cited (Backward Citations)
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