EP0344055A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: Fujitsu Ltd
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Filing: 1989-05-23
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Granted: —
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Expires: 2009-05-23
Abstract
Abstract A semiconductor integrated circuit device includes a semiconductor chip (26), and bonding pads (28, 30; 50, 52, 54; 70, 72, 74) used for interfacing with an external device. The bonding pads are arranged in an outer portion of a chip peripheral area on the semiconductor chip. A pair of N-channel and P-channel transistor areas (32, 34; 56, 58; 76, 78) is provided for two or more neighboring bonding pads among the bonding pads (28, 30; 50, 52, 54; 70, 72, 74), and is arranged in the vicinity of the two or more neighboring bonding pads in the chip peripheral area. The pair of N-channel and P-channel transistor areas (32, 34; 56, 58; 76, 78) is used for forming a peripheral circuit used for interfacing with the external device through the related two or more bonding pads. The peripheral circuit related to the two or more neighboring bonding pads is formed by the pair of N-channel and P-channel transistor areas.
Inventors
- 👤 Yoshiaki Okano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 18:59
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
168 words
A semiconductor integrated circuit device comprising a semiconductor chip (26) having an internal logic circuit area (12) and a chip peripheral area surrounding said internal logic circuit area; and bonding pads (28, 30; 50, 52, 54; 70, 72, 74) used for interfacing with an external device, said bonding pads being arranged in an outer portion of said chip peripheral area, characterized by comprising a pair of N-channel and P-channel transistor areas (32, 34; 56, 58; 76, 78) provided for two or more neighboring bonding pads (28, 30; 50, 52, 54; 70, 72, 74) among said bonding pads and arranged in the vicinity of said two or more neighboring bonding pads in said chip peripheral area, said pair of N-channel and P-channel transistor areas being used for forming a peripheral circuit used for interfacing with said external device through said two or more neighboring bonding pads, said peripheral circuit related to said two or more neighboring bonding pads being formed by said pair of N-channel and P-channel transistor areas.
Claim 2
Dependent Claim
168 words
A semiconductor integrated circuit device comprising a semiconductor chip (26) having an internal logic circuit area (12) and a chip peripheral area surrounding said internal logic circuit area; and bonding pads (28, 30; 50, 52, 54; 70, 72, 74) used for interfacing with an external device, said bonding pads being arranged in an outer portion of said chip peripheral area, characterized by comprising a pair of N-channel and P-channel transistor areas (32, 34; 56, 58; 76, 78) provided for two or more neighboring bonding pads (28, 30; 50, 52, 54; 70, 72, 74) among said bonding pads and arranged in the vicinity of said two or more neighboring bonding pads in said chip peripheral area, said pair of N-channel and P-channel transistor areas being used for forming a peripheral circuit used for interfacing with said external device through said two or more neighboring bonding pads, said peripheral circuit related to said two or more neighboring bonding pads being formed by said pair of N-channel and P-channel transistor areas.
Claim 3
Dependent Claim
80 words
A semiconductor integrated circuit device as claimed in claim 1, characterized in that said pair of N-channel and P-channel transistor areas (32, 34) is provided for two neighboring bonding pads (28, 30), and that one of said paired N-channel and P-channel transistor areas is formed in the vicinity of said two neighboring bonding pads, and the other transistor area is formed on a side of said one transistor area opposite to a side thereof facing said two neighboring bonding pads.
Claim 4
Dependent Claim
46 words
A semiconductor integrated circuit device as claimed in claim 2, characterized in that said pair of N-channel and P-channel transistor areas (32, 34) is arranged side by side in the direction perpendicular to the direction of the arrangement of said two neighboring bonding pads (28, 30).
Claim 5
Dependent Claim
40 words
A semiconductor integrated circuit device as claimed in any of claims 2 to 4, characterized in that each of said paired N-channel and P-channel transistor areas (32, 34) provided for said two neighboring bonding pads (28, 30) is continuously formed.
Claim 6
Dependent Claim
49 words
A semiconductor integrated circuit device as claimed in claim 4, characterized in that the width of each of said paired N-channel and P-channel transistor areas (32, 34) is equal to or smaller than the distance between ends of said two bonding pads (28, 30) other than opposed ends thereof.
Claim 7
Dependent Claim
69 words
A semiconductor integrated circuit device as claimed in any of claims 2 to 5, characterized in that said N-channel transistor area (32) of said pair is formed in the vicinity of said two neighboring bonding pads (28, 30), and said P-channel transistor area (34) of said pair is formed on the side of said N-channel transistor area (32) opposite to the side thereof facing said two neighboring bonding pads.
Claim 8
Dependent Claim
51 words
A semiconductor integrated circuit device as claimed in any of claims 1 to 6, characterized in that said two or more neighboring bonding pads (28, 30; 50, 52, 54; 70, 72, 74) are separated from each other at a minimum separation distance determined in view of working requirements of wire bonding.
Claim 9
Dependent Claim
100 words
A semiconductor integrated circuit device as claimed in claim 1, characterized in that said pair of N-channel and P-channel transistor areas (56, 58; 76, 78) is provided for three neighboring bonding pads of first, second and third bonding pads (50, 52, 54; 70, 72, 74), and that the P-channel transistor area (58, 78) of said pair is formed in the vicinity of said first and second neighboring bonding pads (50, 52; 70, 72)), and said P-channel transistor area (56, 76) of said pair is formed in the vicinity of said second and third neighboring bonding pads (52, 54; 72, 74).
Claim 10
Dependent Claim
48 words
A semiconductor integrated circuit device as claimed in claim 8, characterized in that said pair of N-channel and P-channel transistor areas (56, 58; 76, 78) is arranged side by side along the arrangement of said first, second and third neighboring bonding pads (50, 52, 54; 70, 72, 74).
Claim 11
Dependent Claim
43 words
A semiconductor integrated circuit device as claimed in claim 8 or 9, characterized in that each of said paired N-channel and P-channel transistor areas (56, 58) is considerably wider than each of the first, second and third neighboring bonding pads (50, 52, 54).
Claim 12
Dependent Claim
52 words
A semiconductor integrated circuit device as claimed in any of claims 8 to 10, characterized in that the distance between the neighboring bonding pads among said first, second and third neighboring bonding pads (50, 52, 54) is larger than a minimum separation distance determined in view of working requirements for wire bonding.
Claim 13
Dependent Claim
52 words
A semiconductor integrated circuit device as claimed in any of claims 8 to 11, characterized in that the distance between two neighboring bonding pads among said first, second and third bonding pads (70, 72, 74) is almost identical to a minimum separation distance determined in view of working requirements for wire bonding.
Claim 14
Dependent Claim
82 words
A semiconductor integrated circuit device as claimed in any of claims 1 to 12, characterized in that each of said paired N-channel and P-channel bonding pads (28, 30; 50, 52, 54; 70, 72, 74) comprises a plurality of source and drain areas (32a, 32b, 34a, 34b; 56a, 56b, 56c, 58a, 58b, 58c; 76a, 76b, 76c; 78a, 78b, 78c) alternately arranged in a direction perpendicular to the direction of the arrangement of said bonding pads (28, 30; 50, 52, 54; 70, 72, 74).
Claim 15
Dependent Claim
31 words
A semiconductor integrated circuit device as claimed in any of claims 1 to 13, characterized in that said semiconductor integrated circuit device is a master slice type semiconductor integrated circuit device.
Claim 16
Dependent Claim
86 words
A semiconductor integrated circuit device as claimed in any of claims 1 to 14, characterized by further comprising a gate electrode (42₁ - 42₄; 60, 62; 80, 82) provided for each of said N-channel and P-channel transistor areas (32, 34; 56, 58; 76, 78), and said interconnection lines (38a - 38d; 64a - 64g; 84a - 84g) used for coupling said bonding pads (28, 30; 50, 52, 54; 70, 72, 74), said P-channel and N-channel transistor areas, said gate electrode and said internal logic circuit area.
Claim 17
Dependent Claim
49 words
A semiconductor integrated circuit device as claimed in any of claims 1 to 15, characterized in that said peripheral circuit comprises an input buffer circuit for buffering a signal supplied from said external device through one or more related bonding pads (28, 30; 50, 52, 54; 70, 72, 74).
Claim 18
Dependent Claim
51 words
A semiconductor integrated circuit device as claimed in any of claims 1 to 15, characterized in that said peripheral circuit comprises an output buffer circuit for buffering a signal to be output to said external device through one or more related bonding pads (28, 30; 50, 52, 54; 70, 72, 74).
Claim 19
Dependent Claim
40 words
A semiconductor integrated circuit device as claimed in any of claims 1 to 15, characterized in that said peripheral circuit comprises a bi-directional buffer circuit having the function of outputting and inputting a signal to and from said external device.
Claim 20
Dependent Claim
63 words
A semiconductor integrated circuit device as claimed in any of claims 1 to 15, characterized in that said peripheral circuit comprises a buffer circuit which is provided for each of said two or more related bonding pads (28, 30; 50, 52, 54; 70, 72, 74) and is formed by said pair of N-channel and P-channel transistor areas (32, 34; 56, 58; 76, 78).
References Cited (Backward Citations)
No citation records indexed.
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