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EP0343698A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Process for producing interconnect structures on a semiconductor device, especially on an LSI circuit

Assignee: Koninklijke Philips NV
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Filing: 1989-04-17
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Granted: —
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Expires: 2009-04-17
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Abstract

Abstract Process of the type consisting in obtaining a contact with an active zone (11) carried by a semiconductor substrate (10) by means of conductive pins (18a) located in the contact apertures (16c) of an insulating layer (12), and in then producing a metal interconnection structure (22) effecting the conductive link with the conductive pins (18a). <??>A separation layer (13) is provided between the insulating layer (12) and the conductive layer (18) which can be removed selectively relative to the insulating layer (12). Thus, the insulating layer (12) retains its initial flatness and the conductive pins (18a) have an upper level (20) which stands slightly proud of the level (21) of the insulating layer (12), thus favouring contact between these pins (18a) and the metal interconnection structure (22). <??>Application to large-scale integration microcircuits. <IMAGE>

Inventors

  • 👤 Malcolm Grief
  • 👤 Trung Doan
  • 👤 Hendrikus Van Houtun
  • 👤 Josephus Van Laarhoven

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 14:47
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/032; H10W20/033

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

WO1987004858A1 Cited

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