EP0343537A2
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EP
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Timing generator
Assignee: Advantest Corp
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Filing: 1989-05-19
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Granted: —
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Expires: 2009-05-19
Abstract
Abstract A timing generator for generating arbitrarily delayed pulses, in which, upon each readout of period data from a period data memory (21), a computing section (25) subtracts its accumulated value from delay data read out of a delay data memory (22) and upon inversion of the sign of the subtracted value, the immediately preceding subtracted value is provided to a delayed pulse generator (26), which generates a pulse at the timing corresponding to the subtracted value applied thereto.
Inventors
- 👤 Naoyoshi C/O Advantest Corporation Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 04:00
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31937; G01R31/31917; G01R31/31922; H; H03; H03K; H03K3/00; H03K3/78; H03K5/00; H03K5/13; H03K5/131; H03K2005/00013; H03K2005/0015; H03K2005/00234; H03K2005/00247; H03K2005/0026
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
120 words
A timing generator comprising: a period data memory which stores period data for defining the timing for the generation of timing pulses; a delay data memory which stores delay data for defining delay times relative to the timing for the generation of said timing pulses; computing means whereby, upon each readout of said period data from said period data memory, its accumulated value is subtracted from delay data being output at the time; and delayed pulse generating means which, upon inversion of the sign of the computed value by said computing means, loads thereinto the immediately preceding computed value as delay data and generates a pulse delayed behind the next timing pulse by the value of said loaded delay data.
Claim 2
Dependent Claim
120 words
A timing generator comprising: a period data memory which stores period data for defining the timing for the generation of timing pulses; a delay data memory which stores delay data for defining delay times relative to the timing for the generation of said timing pulses; computing means whereby, upon each readout of said period data from said period data memory, its accumulated value is subtracted from delay data being output at the time; and delayed pulse generating means which, upon inversion of the sign of the computed value by said computing means, loads thereinto the immediately preceding computed value as delay data and generates a pulse delayed behind the next timing pulse by the value of said loaded delay data.
Claim 3
Dependent Claim
71 words
The timing generator of claim 1, further comprising: timing pulse generating means which, upon each application thereto of said period data read out of said period data memory, generates a timing pulse at a time point defined by said period data; and address generating means which responds to said timing pulse from said timing pulse generating means to generate addresses for reading said period data memory and said delay data memory.
Claim 4
Dependent Claim
70 words
The timing generator of claim 1, wherein said computing means includes: subtracting means which subtracts one of its two outputs from the other and outputs the subtracted value and its sign; multiplexer means which is supplied with said subtracted value from said subtracting means and said delay data read out of said delay data memory and selectively outputs one of these inputs; and latch means for latching said subtracted value.
Claim 5
Dependent Claim
107 words
The timing generator of claim 3, further comprising: timing pulse generating means which, upon each application thereto of said period data read out of said period data memory, generates a timing pulse at the timing defined by said period data; address generating means which responds to said timing pulse from said timing pulse generator to generate an address for read out each of said period data memory and said delay data memory; and control means which, upon inversion of the sign of the output of said subtracting means, responds to said timing pulse to generate a control signal for controlling the selective outputting of said multiplexer means.
Claim 6
Dependent Claim
30 words
The timing generator of claim 1, wherein said computing means and said delayed pulse generating means include a plurality of computing sections and a plurality of delayed pulse generators, respectively.
Claim 7
Dependent Claim
78 words
The timing generator of claim 5, further comprising: timing pulse generating means which, upon each application thereto of said period data read out of said period data memory, generates a timing pulse at the timing defined by said period data; and control means which responds to said timing pulse to generate addresses to be applied to said period data memory and said delay data memory and a control signal to be applied to each of said computing sections.
Claim 8
Dependent Claim
44 words
The timing generator of claim 6, wherein said control means includes means which responds to said timing pulse to generate a control signal for loading said delay data read out of said delay data memory into said computing sections in a sequential, cyclic order.
Claim 9
Dependent Claim
119 words
The timing generator of claim 7, wherein each of said computing section includes first latch means which responds to said loading control signal to latch said delay data from said delay data memory, subtracting means which subtracts one of its two inputs from the other and outputs the subtracted value and its sign, a multiplexer which is supplied with said subtracted value from said subtracting means and the output of said first latch means and outputs either one of them in accordance with a selection control signal from control means, and second latch means for storing the output of said multiplexer, said period data from said period data memory being applied to the other input of said subtracting means.
References Cited (Backward Citations)
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