Method of manufacturing a semiconductor device

Claim 2

In a Bi-MOS semiconductor device having a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate, the improvement comprising: a plurality of element isolation regions each thereof including a first semiconductor region formed in said semi­conductor substrate and having the same type of conductivity as said semiconductor substrate, and a thick insulation layer formed on said first semiconductor region, and wherein at least one of an emitter electrode and a collector electrode formed in said bipolar device, gate elec­trodes formed in said MOS devices, a low-resistivity polycrystalline silicon layer formed by a buried contact from one of said MOS devices, and a high-resistivity portion formed by a highresistivity polycrystalline silicon layer connected to said low-resistivity polycrystalline silicon layer are formed from a polycrystalline silicon layer formed by the same layer formation.

Claim 3

In a Bi-MOS semiconductor device having a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate, the improvement comprising: a plurality of element isolation regions each thereof including a first semiconductor region formed in said semi­conductor substrate and having the same type of conductivity as said semiconductor substrate, a second semiconductor region formed in a semiconductor layer formed on said semiconductor substrate surface and different in conductivity type from said semiconductor substrate, said second semiconductor region having a bottom portion thereof in contact with said first semiconductor region and having the same type of conductivity as said semiconductor substrate, and a thick insulation layer formed on said second semiconductor region, and wherein at least one of an emitter electrode and a collector electrode formed in said bipolar device, gate electrodes formed in said MOS devices, a low-resistivity polycrystalline silicon layer formed by a buried contact from one of said MOS devices, and a high-resistivity portion formed by a high-resistivity polycrystalline silicon layer connected to said low-resistivity polycrystalline silicon layer are formed from a polycrystalline layer formed by the same layer formation.

Claim 4

In a Bi-MOS semiconductor device having a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate, the improvement comprising: a plurality of element isolation regions each thereof including a first semiconductor region formed in said semi­conductor substrate and having the same type of conductivity as said semiconductor substrate, a second semiconductor region formed in a semiconductor layer formed on said semiconductor substrate surface and different in conductivity type from said semiconductor substrate, said second semiconductor region having a bottom portion thereof in contact with said first semiconductor region and having the same type of conductivity as said semiconductor substrate, and a thick insulation layer formed on said second semiconductor region, and wherein at least one of an emitter electrode and a collector electrode formed in said bipolar device, gate electrodes formed in said MOS devices, a low-resistivity polycrystalline silicon layer formed by a buried contact from one of said MOS devices, and a high-resistivity portion formed by a high-resistivity polycrystalline silicon layer connected to said low-resistivity polycrystalline silicon layer are formed from a polycrystalline layer formed by the same layer formation.

Claim 5

A semiconductor device according to claim 1 or 2, wherein said emitter electrode is composed of said polycrystalline silicon layer, and said collector electrode connected to a collector lead-out region is a metal layer.

Claim 6

A semiconductor device according to claim 1 or 2, wherein a metal silicide layer consists from Ti, W, Mo, Pt, Co and so forth is formed on each of diffusion layers forming source and drain regions of said MOS devices and base regions of said bipolar device in said Bi-MOS semiconductor device and said polycrystalline silicon layer excluding said high-resistivity region and formed by said same layer formation.

Claim 7

In a method of manufacturing a Bi-MOS semiconductor device having a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate, the improvement comprising the steps of: forming a plurality of element isolation regions each thereof being formed by forming in said semiconductor substrate a first semiconductor region of the same type of conductivity as said semiconductor substrate and selectively forming a thick insulation layer on said first semiconductor region; forming a thin insulation layer on a plurality of device forming regions surrounded by said element isolation regions and then forming simultaneously openings for one of emitter region and collector lead-out region and an opening for buried contact; forming a polycrystalline silicon layer forming at least one of an emitter electrode and a collector electrode in said bipolar device, gate electrodes of said MOS devices a low-­resistivity polycrystalline silicon layer formed by a buried contact from one of said MOS devices, and a high-resistivity portion formed by a high-resistivity polycrystalline silicon layer connected to said low-resistivity polycrystalline silicon layer by the same growing and processing operations; and diffusing an impurity from said polycrystalline silicon layer to form said emitter region together with a buried contact region or to form said collector lead-out region together with a buried contact region.

Claim 8

In a method of manufacturing a Bi-MOS semiconductor device having a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate, the improvement comprising the steps of: forming a plurality of element isolation regions each thereof being formed by forming in said semiconductor substrate a first semiconductor region of the same type of conductivity as said semiconductor substrate and selectively forming a thick insulation layer on said first semiconductor region; forming a thin insulation layer on a plurality of device forming regions surrounded by said element isolation regions and then forming simultaneously openings for one of emitter region and collector lead-out region and an opening for buried contact; forming a polycrystalline silicon layer forming at least one of an emitter electrode and a collector electrode in said bipolar device, gate electrodes of said MOS devices a low-­resistivity polycrystalline silicon layer formed by a buried contact from one of said MOS devices, and a high-resistivity portion formed by a high-resistivity polycrystalline silicon layer connected to said low-resistivity polycrystalline silicon layer by the same growing and processing operations; and diffusing an impurity from said polycrystalline silicon layer to form said emitter region together with a buried contact region or to form said collector lead-out region together with a buried contact region.

Claim 9

In a method of manufacturing A Bi-MOS semiconductor device including a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate, the improvement comprising the steps of: forming a plurality of element isolation regions each thereof being formed by forming in said semiconductor substrate a first semiconductor region of the same type of conductivity as said semiconductor substrate, forming a second semiconductor region of the same type of conductivity as said semiconductor substrate in a semiconductor layer formed on said semiconductor substrate surface and different in conductivity type from said semiconductor substrate such that said second semiconductor region has a bottom portion thereof contacted with said first semiconductor layer, and selectively forming a thick insulation layer on said second semiconductor region; forming a thin insulation layer on device forming regions surrounded by said element isolation regions and then forming simultaneously openings for one of emitter region and collector lead-out region and an opening for buried contact; forming a polycrystalline silicon layer forming at least one of an emitter electrode and a collector electrode in said bipolar device, gate electrodes of said MOS devices a low-­resistivity polycrystalline silicon layer formed by a buried contact from one of said MOS devices and a high-resistivity portion formed by a high-resistivity polycrystalline silicon layer connected to said low-resistivity polycrystalline silicon layer by the same growing and processing operations; and diffusing an impurity from said polycrystalline silicon layer to form said emitter region together with a buried contact region or to form said collector lead-out region together with a buried contact region.

Claim 10

In a method of manufacturing A Bi-MOS semiconductor device including a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate, the improvement comprising the steps of: forming a plurality of element isolation regions each thereof being formed by forming in said semiconductor substrate a first semiconductor region of the same type of conductivity as said semiconductor substrate, forming a second semiconductor region of the same type of conductivity as said semiconductor substrate in a semiconductor layer formed on said semiconductor substrate surface and different in conductivity type from said semiconductor substrate such that said second semiconductor region has a bottom portion thereof contacted with said first semiconductor layer, and selectively forming a thick insulation layer on said second semiconductor region; forming a thin insulation layer on device forming regions surrounded by said element isolation regions and then forming simultaneously openings for one of emitter region and collector lead-out region and an opening for buried contact; forming a polycrystalline silicon layer forming at least one of an emitter electrode and a collector electrode in said bipolar device, gate electrodes of said MOS devices a low-­resistivity polycrystalline silicon layer formed by a buried contact from one of said MOS devices and a high-resistivity portion formed by a high-resistivity polycrystalline silicon layer connected to said low-resistivity polycrystalline silicon layer by the same growing and processing operations; and diffusing an impurity from said polycrystalline silicon layer to form said emitter region together with a buried contact region or to form said collector lead-out region together with a buried contact region.

Claim 11

A method according to claim 5 or 6 wherein said emitter electrode connected to said emitter region is formed by using said polycrystalline silicon layer said collector electrode connected to said collector lead-out region is formed by using a metal layer.

Claim 12

A method according to claim 5 or 6, wherein after said step of diffusing an impurity from said polycrystalline silicon layer to a low-resistivity polycrystalline silicon layer formed by a buried contact from one of said MOS devices, a metal silicide layer consists from Ti, W, Mo, Pt, Co is formed in a self-aligning manner on diffusion layers forming source and drain regions of said MOS devices and base regions of said bipolar device in said Bi-MOS semiconductor device and said polycrystalline silicon layer excluding said high-resistivity region.