Mosfet power switch arrangements

Claim 1

A MOSFET power switch arrangement including a MOSFET transistor (1) and a semiconductor switch (2) electrically connected to the gate electrode (G) of the MOSFET and thermally connected to the MOSFET, the arrangement being such that if the MOSFET is on and a load (3) connected thereto is in normal condition then the semiconductor switch (2) is off, such that if the MOSFET is on and the load (3) is in short-circuit condition the heat generated in the MOSFET causes the semiconductor switch (2) to turn on when it goes above a predetermined temperature, and such that the turned on condition of the semiconductor switch (2) causes the MOSFET to turn off, the arrangement also including means for suppressing voltage transients generated by parasitic wiring inductances (7,8) in the power feeds to the MOSFET drain (D) and source electrodes (S) when it turns off responsive to the semiconductor switch (2) turning on, characterised in that the voltage transient suppression means includes first suppression means (11,12) for limiting to a predetermined value the drain-gate voltage (Vdg) due to the initial parasitically induced voltage excursion at the drain electrode (D) when the semiconductor switch (2) turns on, and second suppression means (11,12,2,10,5) responsive to the initial parasitically induced voltage excursion at the source electrode (S)when the semiconductor switch (2) turns on to establish an initial gate-source voltage (Vgs) sufficient to keep the MOSFET (1) on but not greater than a predetermined value, such that the voltage transient suppression means allows the transient energy to dissipate by current conduction through the MOSFET with the turn-off time of the MOSFET being dependent on the values of said parasitic wiring inductances (7,8).