Programmable logic device with programmable word line connections

Claim 2

A programmable logic device for pro­ducing a plurality of first signals, each of which is a programmable logical function of a plurality of second signals, each of which is applied to a respec­tive one of a plurality of word line conductors, said programmable logic device comprising: a plurality of first P-term line con­ductors, each of which is programmably interconnect­able to each of said word line conductors for produc­ing on each of said first P-term line conductors a third signal which is a logical function of the second signals applied to the word line conductors to which that first P-term line conductor is interconnected; means for logically combining said third signals to produce a first of said first signals; at least one second P-term line con­ductor which is programmably interconnectable to each of said word line conductors for producing on said second P-term line conductor a second of said first signals which is a logical function of the second signals applied to the word line conductors to which said second P-term line conductor is inter­connected; means for receiving an input signal applied to the programmable logic device; and switch means for applying either the second of said first signals or said input signal to one of said word line conductors as the second signal applied to that word line conductor.

Claim 3

The apparatus defined in claim 1 fur­ther comprising: at least one third P-term line con­ductor which is programmably interconnectable to each of said word line conductors for producing on said third P-term line conductor a third of said first signals which is a logical function of the second signals applied to the word line conductors to which said third P-term line conductor is inter­connected; and means for applying the third of said first signals to said switch means for controlling said switch means to apply either the second of said first signals or said input signal to said one of said word line conductors.

Claim 4

The apparatus defined in claim 2 fur­ther comprising: at least two of said second P-term line conductors; and means for forming parallel true and complement signal versions of said input signal; and wherein said switch means applies either (1) the output signals of said two of said second P-term line conductors or (2) said true and complement signal versions of said input signal to two of said word line conductors, respectively.

Claim 5

The apparatus defined in claim 3 fur­ther comprising: at least one third P-term line con­ductor which is programmably interconnectable to each of said word line conductors for producing on said third P-term line conductor a third of said first signals which is a logical function of the second signals applied to the word line conductors to which said third P-term line conductor is inter­connected; and means for applying the third of said first signals to said switch means for controlling said switch means to apply either (1) the output signals of said two of said second P-term line con­ductors or (2) said true and complement signal versions to said two of said word line conductors, respectively.

Claim 6

The apparatus defined in claim 1 wherein said means for receiving an input signal includes a Schmitt trigger for noise filtering said input signal.

Claim 7

A programmable logic device for pro­ducing a plurality of first signals, each of which is a programmable logical function of a plurality of second signals, each of which is applied to a respec­tive one of a plurality of word line conductors, said programmable logic device comprising: first and second macrocells, each including: (a) a plurality of first P-term line conductors, each of which is programmably inter­connectable to each of said word line conductors for producing on each of said first P-term line conductors a third signal which is a logical function of the second signals applied to the word line conductors to which that first P-term line conductor is interconnected; (b) means for logically combining said third signals to produce a first of said first signals; and (c) at least one second P-term line conductor which is programmably interconnectable to each of said word line conductors for produc­ing on said second P-term line conductor a second of said first signals which is a logical function of the second signals applied to the word line conductors to which said second P-term line conductor is interconnected; means for receiving an input signal applied to the programmable logic device; means associated with said first macro­cell for applying the signal on said second P-term line conductor of said first macrocell to a first of said word line conductors as the second signal applied to that word line conductor; and switch means associated with second macrocell for applying either the signal on said second P-term line conductor of said second macrocell or said input signal to a second of said word line conductors as the second signal applied to that word line conductor.

Claim 8

A programmable logic device for pro­ducing a plurality of first signals, each of which is a programmable logical function of a plurality of second signals, each of which is applied to a respec­tive one of a plurality of word line conductors, said programmable logic device comprising: first and second macrocells, each including: (a) a plurality of first P-term line conductors, each of which is programmably inter­connectable to each of said word line conductors for producing on each of said first P-term line conductors a third signal which is a logical function of the second signals applied to the word line conductors to which that first P-term line conductor is interconnected; (b) means for logically combining said third signals to produce a first of said first signals; and (c) at least one second P-term line conductor which is programmably interconnectable to each of said word line conductors for produc­ing on said second P-term line conductor a second of said first signals which is a logical function of the second signals applied to the word line conductors to which said second P-term line conductor is interconnected; means for receiving an input signal applied to the programmable logic device; means associated with said first macro­cell for applying the signal on said second P-term line conductor of said first macrocell to a first of said word line conductors as the second signal applied to that word line conductor; and switch means associated with second macrocell for applying either the signal on said second P-term line conductor of said second macrocell or said input signal to a second of said word line conductors as the second signal applied to that word line conductor.

Claim 9

The apparatus defined in claim 6 wherein said means for receiving an input signal is alternatively usable for conveying a signal from the programmable logic device as an output signal; and wherein said programmable logic device further com­prises output driver means for selectively applying the first of said first signals of said first macro­cell to said means for receiving as said output signal.

Claim 10

The apparatus defined in claim 7 wherein each of said macrocells further includes at least one third P-term line conductor which is programmably interconnectable to each of said word line conductors for producing on said third P-term line conductor a third of said first signals which is a logical function of the second signals applied to the word line conductors to which said third P-term line conductor is interconnected; wherein said first macrocell further includes means for applying the signal on said third P-term line conductor of said first macrocell to said output driver means for con­trolling whether said output driver means applies a signal to said means for receiving as said output signal; and wherein said second macrocell further includes means for applying the signal on said third P-term line conductor of said second macrocell to said switch means for controlling whether said switch means applies the signal on said second P-term line conductor of said second macrocell or said input signal to said second word line conductor.

Claim 11

The apparatus defined in claim 6 further comprising: means associated with said first macro­cell for applying the first of said first signals of said first macrocell to a third of said word line conductors as the second signal applied to that word line conductor; and means associated with said second macrocell for applying the first of said first signals of said second macrocell to a fourth of said word line conductors as the second signal applied to that word line conductor.

Claim 12

The apparatus defined in claim 6 wherein said means for receiving an input signal includes a Schmitt trigger for filtering said input signal.

Claim 13

In a programmable logic device having (1) a plurality of word line conductors; (2) a plurality of P-term line conductors, each of which is programmably interconnectable to at least some of said word line conductors for producing on each P-term line conductor a signal which is a logical function of the signals on the word line conductors to which that P-term line conductor is interconnected; and (3) a clock signal utilization device for processing a signal derived from at least one first P-term line conductor in accordance with an applied clock signal, the improvement comprising: means for providing a synchronous clock signal; means responsive to said synchronous clock signal for providing an inverted version of said synchronous clock signal; means responsive to the signal on at least one second P-term line conductor for providing an asynchronous clock signal which is a logical func­tion of the signal on said second P-term line con­ductor; and programmable means for selecting one of said synchronous clock signal, said inverted version of said synchronous clock signal, and said asynchronous clock signal as the clock signal applied to said clock signal utilization device.

Claim 14

In a programmable logic device having (1) a plurality of word line conductors; (2) a plurality of P-term line conductors, each of which is programmably interconnectable to at least some of said word line conductors for producing on each P-term line conductor a signal which is a logical function of the signals on the word line conductors to which that P-term line conductor is interconnected; and (3) a clock signal utilization device for processing a signal derived from at least one first P-term line conductor in accordance with an applied clock signal, the improvement comprising: means for providing a synchronous clock signal; means responsive to said synchronous clock signal for providing an inverted version of said synchronous clock signal; means responsive to the signal on at least one second P-term line conductor for providing an asynchronous clock signal which is a logical func­tion of the signal on said second P-term line con­ductor; and programmable means for selecting one of said synchronous clock signal, said inverted version of said synchronous clock signal, and said asynchronous clock signal as the clock signal applied to said clock signal utilization device.