EP0337676A2
Expired / Lapsed
EP
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Programmable logic array
Assignee: Fujitsu Ltd
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Filing: 1989-04-07
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Granted: —
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Expires: 2009-04-07
Abstract
Abstract A programmable logic array includes a programmable logic array (5₁ - 5 n , 9, 11) being precharged and discharged in synchronism with a clock signal (CLKi) supplied thereto and outputting an operation result with respect to input data supplied thereto. The programmable logic array also includes a circuit (6₁ - 6 n , 7₁ - 7 n , 8) connected to the programmable logic array, for holding the programmable logic array in a precharged state by setting the clock signal to a fixed level when the programmable logic array is not selected and for switching the programmable logic array to a discharged state by supplying the clock signal the programmable logic array when the programmable logic array is selected, so that the programmable logic array is discharged on the basis of the contents of the input data when selected.
Inventors
- 👤 Takayoshi Taniai
- 👤 Tadashi Saitoh
- 👤 Yasuhiro Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 14:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/0008; H03K19/0016; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
141 words
A programmable logic array comprising a programmable logic array (5₁ - 5 n , 9, 11) being precharged and discharged in synchronism with a clock signal (CLKi) supplied thereto and outputting an operation result with respect to input data supplied thereto, characterized in that said programmable logic array comprises means (6₁ - 6 n , 7₁ - 7 n , 8) connected to said programmable logic array, for holding the programmable logic array in a precharged state by setting said clock signal to a fixed level when said programmable logic array is not selected and for switching said programmable logic array to a discharged state by supplying said clock signal said programmable logic array when said programmable logic array is selected, so that said programmable logic array is discharged on the basis of the contents of said input data when selected.
Claim 2
Dependent Claim
141 words
A programmable logic array comprising a programmable logic array (5₁ - 5 n , 9, 11) being precharged and discharged in synchronism with a clock signal (CLKi) supplied thereto and outputting an operation result with respect to input data supplied thereto, characterized in that said programmable logic array comprises means (6₁ - 6 n , 7₁ - 7 n , 8) connected to said programmable logic array, for holding the programmable logic array in a precharged state by setting said clock signal to a fixed level when said programmable logic array is not selected and for switching said programmable logic array to a discharged state by supplying said clock signal said programmable logic array when said programmable logic array is selected, so that said programmable logic array is discharged on the basis of the contents of said input data when selected.
Claim 3
Dependent Claim
55 words
A programmable logic array as claimed in claim 1, characterized in that said programmable logic array (11) is divided into a plurality of sub-programmable logic arrays (5₁ - 5 n ), and said means (6₁ - 6 n , 7₁ - 7 n ) is provided for each of the plurality of sub-programmable logic arrays.
Claim 4
Dependent Claim
91 words
A programmable logic array as claimed in claim 2, characterized in that said means (6₁ - 6 n , 7₁ - 7 n ) provided for each of the sub-programmable logic arrays comprises decoder means (6₁ - 6 n ) for decoding said input data to determine whether or not the corresponding sub-programmable logic array is selected, and clock control means, connected to said decoder means (7₁ - 7 n ), for supplying the corresponding sub-programmable logic array with said clock signal only when the corresponding sub-programmable logic array is selected.
Claim 5
Dependent Claim
27 words
A programmable logic array as claimed in claim 3, characterized in that said decoder means (6₁ - 6 n , decodes a part of said input data.
Claim 6
Dependent Claim
63 words
A programmable logic array as claimed in claims 3 and 4, characterized in that only when the corresponding sub-programmable logic array is selected, the related clock control means (12i) supplies said corresponding sub-programmable logic array with said clock signal (CLKi) during a time where a read signal (RD) defining a timing for outputting said operation result is supplied to said clock control means.
Claim 7
Dependent Claim
66 words
A programmable logic array as claimed in claim 5, characterized in that said clock control means (12i) comprises an NAND gate (12i), which receives an external clock signal ( CLK ) and said read signal (RD), and which is connected to the corresponding decoder means (6i), and that said NAND gate (12i) generates said clock signal (CLKi) from said external clock signal and said read signal.
Claim 8
Dependent Claim
47 words
A programmable logic array as claimed in any of claims 2 to 6, characterized in that said programmable logic array (11) is divided into the plurality of sub-programmable logic arrays (5₁ - 5 n ), depending on functions (A - J) achieved by said programmable logic array.
Claim 9
Dependent Claim
26 words
A programmable logic array as claimed in claim 7, characterized in that said sub-programmable logic arrays (5₁ - 5 n ) present a plurality of functions.
Claim 10
Dependent Claim
23 words
A programmable logic array as claimed in claim 8, characterized in that said input data includes information on functions requested to be executed.
Claim 11
Dependent Claim
81 words
A programmable logic array as claimed in any of claims 1 to 9, characterized in that said programmable logic array comprises precharge transistors (TRp, TRp₁, TRp′) and discharge transistors (TRd, TRd₁, TRd′), and that said means precharges said programmable logic array through said precharge transistors when said programmable logic array is not selected, and allows said programmable logic array to be discharged through said discharge transistor depending on the contents of said input data when said programmable logic array is selected
Claim 12
Dependent Claim
39 words
A programmable logic array as claimed in any of claims 1 to 10, characterized in that said decoder means (6₁ - 6 n ) comprises an inverter (INV10 - INV15, INV16 - INV20), and an AND gate (51 52).
Claim 13
Dependent Claim
67 words
A programmable logic array as claimed in any of claims 2 to 11, characterized in that the plurality of sub-programmable logic arrays (5₁ - 5 n ) have output terminals (OUT) through which corresponding operation results are output, and said output terminals of the plurality of sub-programmable logic arrays are coupled to corresponding transistors (14i) which are mutually connected to thereby form a wired OR logic output.
Claim 14
Dependent Claim
46 words
A programmable logic array as claimed in any of claims 2 to 12, characterized by further comprising precharge means (6₁′, 16) for precharging said wired OR output during a time when said programmable logic array composed of the plurality of sub-programmable logic arrays is not selected.
Claim 15
Dependent Claim
30 words
A programmable logic array as claimed in any of claims 2 to 12, characterized in that the plurality of sub-programmable logic arrays (5₁ - 5 n ) are periodically selected.
Claim 16
Dependent Claim
40 words
A programmable logic array as claimed in any of claims 1 to 14, characterized in that said means (7₁ - 7 n , 8) generates a fixed voltage of a high level when said programmable logic array is not selected.
Claim 17
Dependent Claim
51 words
A programmable logic array as claimed in any of claims 1 to 15, characterized in that said programmable logic array (5₁ - 5 n , 9, 11) is alternately switched to said discharged state and precharged state in synchronism with said clock signal only when said programmable logic array is selected.
Claim 18
Dependent Claim
102 words
A programmable logic array as claimed in claim 1, characterized in that said means (9) receives an external clock signal ( CLK ) and a read signal (RD), and that when said read signal is supplied thereto, said means supplies said programmable logic array with said external clock signal ( CLK ) as said clock signal, and thereby switches said programmable logic array to the discharged state where said programmable logic array is discharged based on the contents of said input data, and said means holds said programmable logic array in the precharged state when no signal is supplied to said means.
References Cited (Backward Citations)
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