EP0337393A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
2-cell/1-bit type EPROM
Assignee: Toshiba Corp
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Filing: 1989-04-11
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Granted: —
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Expires: 2009-04-11
Abstract
Abstract The first input terminal (N1) of a differential amplification type sense amplifier (1) is connected to a first memory cell array (MCA1) and the second input terminal (N2) thereof is connected to a second memory cell array (MCA2). Each of the first and second memory cell arrays (MCA1, MCA2) is formed of a plurality of memory cells (MC, MC ) arranged in a matrix form. Each of the memory cells (MC) in the first memory cell array (MCA1) and a corresponding one of the memory cells ( MC ) in the second memory cell array (MCA2) are provided in the form of pair for each bit. Complementary data is programmed into the paired memory cells (MC, MC ) according to programming data (Din). In the data readout operation, the potential of data read out from the paired memory cells (MC, MC ) is amplified by means of the differential amplification type sense amplifier (1). First and second loads (4-1, 7-1, 8-1, 4-2, 7-2, 8-2) are connected to the first and second input terminals (N1, N2) of the differential amplification type sense amplifier (1). The mutual conductances of the first and second loads (4-1, 7-1, 8-1, 4-2, 7-2, 8-2) are controlled so as to set the potential difference between the potentials of data read out from the paired memory cells (MC, MC ) selected in the first and second memory cell arrays (MCA1, MCA2) smaller in the verify mode than in the normal readout mode.
Inventors
- 👤 Shigeru Atsumi
- 👤 Sumio Tanaka
- 👤 Junichi Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 08:58
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/04; G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C16/04; G11C16/0408; G11C16/0441; G11C16/10; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
286 words
A semiconductor memory device comprising a first memory cell array (MCA1) having nonvolatile memory cells (MC) arranged in a matrix form; a second memory cell array (MCA2) having nonvolatile memory cells ( MC ) arranged in a matrix form and selected in combination with the respective memory cells (MC) of said first memory cell array (MCA1) in a paired form; programming means (5-1, 5-2, 6-1, 6-2, 10) for setting one of the paired memory cells (MC, MC ) selected from said first and second memory cell arrays (MCA1, MCA2) into the programmed state and the other into the non-progammed state according to the programming data and thus programming complementary data into the paired memory cells (MC, MC ) selected from said first and second memory cell arrays (MCA1, MCA2); sense amplifier means (1) for determining stored data by comparing data read out from the selected memory cell (MC) in said first memory cell array (MCA1) with data read out from the selected memory cell ( MC ) in said second memory cell array (MCA2); characterized by further comprising latch means (12, 13, 14, 9-1, 9-2, 11) for temporarily storing input programming data when complementary data is programmed into a pair of selected memory cells (MC, MC ) of said first and second memory cell arrays (MCA1, MCA2); and criterion setting means (4-1, 4-2, 7-1, 7-2, 8-1, 8-2, 15-1, 15-2, 16-1, 16-2, 19) for setting a criterion severer in the verify operation effected immediately after complementary data has been programmed into the memory cells (MC, MC ) of said first and second memory cell arrays (MCA1, MCA2) according to data latched in said latch means (12, 13, 14, 8-1, 9-2, 11) than in the normal readout operation.
Claim 2
Dependent Claim
286 words
A semiconductor memory device comprising a first memory cell array (MCA1) having nonvolatile memory cells (MC) arranged in a matrix form; a second memory cell array (MCA2) having nonvolatile memory cells ( MC ) arranged in a matrix form and selected in combination with the respective memory cells (MC) of said first memory cell array (MCA1) in a paired form; programming means (5-1, 5-2, 6-1, 6-2, 10) for setting one of the paired memory cells (MC, MC ) selected from said first and second memory cell arrays (MCA1, MCA2) into the programmed state and the other into the non-progammed state according to the programming data and thus programming complementary data into the paired memory cells (MC, MC ) selected from said first and second memory cell arrays (MCA1, MCA2); sense amplifier means (1) for determining stored data by comparing data read out from the selected memory cell (MC) in said first memory cell array (MCA1) with data read out from the selected memory cell ( MC ) in said second memory cell array (MCA2); characterized by further comprising latch means (12, 13, 14, 9-1, 9-2, 11) for temporarily storing input programming data when complementary data is programmed into a pair of selected memory cells (MC, MC ) of said first and second memory cell arrays (MCA1, MCA2); and criterion setting means (4-1, 4-2, 7-1, 7-2, 8-1, 8-2, 15-1, 15-2, 16-1, 16-2, 19) for setting a criterion severer in the verify operation effected immediately after complementary data has been programmed into the memory cells (MC, MC ) of said first and second memory cell arrays (MCA1, MCA2) according to data latched in said latch means (12, 13, 14, 8-1, 9-2, 11) than in the normal readout operation.
Claim 3
Dependent Claim
100 words
A semiconductor memory device according to claim 1, characterized in that said criterion setting means includes potential difference reducing means (14-1, 7-1, 7-2, 8-1, 8-2, 15-1, 15-2, 16-1, 16-2) for setting the potential difference between the potentials of data read out from selected ones of the memory cells (MC, MC ) in said first and second memory cell arrays (MCA1 and MCA2) smaller in the verify operation effected immediately after complementary data has been programmed into the memory cells (MC, MC ) of said first and second memory cell arrays (MCA1 and MCA2) than that in the normal readout operation.
Claim 4
Dependent Claim
65 words
A semiconductor memory device according to claim 1, characterized in that said criterion setting means includes means (4-1, 4-2, 7-1, 7-2, 8-1, 8-2) for increasing the conductance of a load of the input terminal of said sense amplifier means (1) connected to one of said first and second memory cell arrays (MCA1 and MCA2) which is associated with the non-programmed section in the verify mode.
Claim 5
Dependent Claim
111 words
A semiconductor memory device according to claim 3, characterized in that said means for increasing the conductance of said load includes first and second load means (4-1, 4-2) respectively connected to first and second input terminals (N1, N2) of said sense amplifier means (1); and third and fourth load means (7-1, 8-1, 7-2, 8-2) respectively connected to the first and second input terminals (N1, N2) of said sense amplifier means (1); one of said third and fourth load means (7-1, 8-1, 7-2, 8-2) being set into the non-operative state while the other is set in the operative state according to an output of said latch means (12, 13, 14, 9-1, 11).
Claim 6
Dependent Claim
35 words
A semiconductor memory device according to claim 4, characterized in that each of said first and second load means includes an enhancement type P-channel MOS transistor (4-1, 4-2) whose gate and drain are connected together.
Claim 7
Dependent Claim
182 words
A semiconductor memory device according to claim 4, characterized in that said third load means includes a first MOS transistor (8-1) of P-channel enhancement type whose gate and drain are commonly connected to the first input terminal (N1) of said sense amplifier means (1); and a second MOS transistor (7-1) of P-channel enhancement type whose current path is connected between the source of said first MOS transistor (8-1) and a first potential supplying source (Vcc) and whose conduction state is controlled by the output of said latch means (12, 13, 14, 9-1, 9-2, 11), and said fourth load means includes a third MOS transistor (8-2) of P-channel enhancement type whose gate and drain are commonly connected to the second input terminal (N2) of said sense amplifier means (1); and a fourth MOS transistor (7-2) of P-channel enhancement type whose current path is connected between the source of said third MOS transistor (8-2) and said first potential supplying source (Vcc) and whose conduction state is controlled by an inverted signal of the output of said latch means (12, 13, 14, 9-1, 9-2, 11).
Claim 8
Dependent Claim
60 words
A semiconductor memory device according to claim 1, characterized in that said criterion setting means includes leak means (15-1, 15-2, 16-1, 16-2) for increasing the leak current in the input terminal of said sense amplifier means connected to one of said first and second memory cell arrays (MCA1, MCA2) which is associated with the non-programmed side in the verify operation.
Claim 9
Dependent Claim
152 words
A semiconductor memory device according to claim 7, characterized in that said leak means includes first switching means (15-1) which is connected at one end to the first input terminal (N1) of said sense amplifier means (1) and whose switching position is controlled based on an inverted signal of the output of said latch means (12, 13, 14, 9-1, 9-2, 11); a first leak current source (16-1) connected between the other end of said first switching means (15-1) and a second potential supplying source (Vss); second switching means (15-2) which is connected at one end to the second input terminal (N2) of said sense amplifier means (1) and whose switching position is controlled based on the output of said latch means (12, 13, 14, 9-1, 9-2, 11); and a second leak current source (16-2) connected between the other end of said second switching means (15-2) and said second potential supplying source (Vss).
Claim 10
Dependent Claim
25 words
A semiconductor memory device according to claim 8, characterized in that each of said first and second switching means includes a MOS transistor (15-1, 15-2).
Claim 11
Dependent Claim
60 words
A semiconductor memory device according to claim 1, characterized in that said criterion setting means includes a sense amplifier (19) whose first input terminal (N3) is applied with a potential corresponding to data read out from a programmed one of the memory cells (MC or MC ) and whose second input terminal (N4) is applied with a reference potential (VR).
Claim 12
Dependent Claim
22 words
A semiconductor memory device according to claim 10, characterized in that said sense amplifier includes a differential amplification type sense amplifier (19).
Claim 13
Dependent Claim
78 words
A semiconductor memory device according to claim 11, characterized in that the reference potential (VR) applied to the second input terminal (N4) of said differential amplification type sense amplifier (19) is set higher than the potential of data read out from the memory cell ( MC of MC) on the non-programmed side in the normal readout operation and lower than the potential of data read out from the memory cell (MC or MC ) on the programmed side.
Claim 14
Dependent Claim
21 words
A semiconductor memory device according to claim 10, characterized in that said sense amplifier includes a feedback type sense amplifier (19).
Claim 15
Dependent Claim
152 words
A semiconductor memory device according to claim 1, characterized in that said programming means includes a first MOS transistor (5-1) whose current path is connected at one end to a programming power source terminal (Vpp) and at the other end to said first memory cell array (MCA1); first level shifter means (6-1) for shifting the potential of programmed data to the potential level of the programming voltage (Vpp) and applying the potential to the gate of said first MOS transistor (5-1); a second MOS transistor (5-2) whose current path is connected at one end to said programming power source terminal (Vpp) and at the other end to said second memory cell array (MCA2); and second level shifter means (6-2) for shifting the potential of an inverted signal of programmed data to the potential level of the programming voltage (Vpp) and applying the potential to the gate of said second MOS transistor (5-2).
Claim 16
Dependent Claim
32 words
A semiconductor memory device according to claim 14, characterized in that said each of said frst and second level shifter means includes an inverter (6-1, 6-2) operated on the programming voltage (Vpp).
Claim 17
Dependent Claim
227 words
A semiconductor memory device according to claim 1, characterized in that said latch means includes a first MOS transistor (12) whose current path receives programming data (Din) at one end and whose gate is supplied with a latch pulse (LA) kept at a high level for a preset period of time prior to the data programming operation; a latch circuit (13) whose input terminal is connected to the other end of current path of said first MOS transistor (12); a second MOS transistor (14) whose current path is connected at one end to the output terminal of said latch circuit (13) and whose gate is supplied with a first control signal (SVpp) set at a high level in the data programming mode and verify mode; a first NAND gate (9-1) whose first input terminal is connected to the other end of the current path of said second MOS transistor (14) and whose second input terminal is supplied with a second control signal (PV) set at a high level in the programming and verify modes and at a low level in the normal readout mode; and a second NAND gate (9-2) whose first input terminal is connected to the other end of the current path of said second MOS transistor (14) and whose second input terminal is supplied with an inverted signal of the second control signal (PV).
Claim 18
Dependent Claim
23 words
A semiconductor memory device according to claim 1, characterized in that said sense amplifier means includes a differential amplification type sense amplifier (19).
References Cited (Backward Citations)
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