EP0336977A1
Expired / Lapsed
EP
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Semiconducteur device and method of producing the same
Assignee: Panasonic Holdings Corp
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Filing: 1988-10-06
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Granted: —
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Expires: 2008-10-06
Abstract
Abstract A semiconducteur device includes a semiconductor substrate of a first conductivity type in which a well of a second conductivity type is surrounded by a buried layer of a high concentration of the first conductivity type formed in a deep region beneath the well and by a well of the first conductivity type in a shallow region formed continuously in the buried layer of a high concentration in a self-aligned manner in the substrate. Therefore, the potential of the high-concentration buried layer is easily fixed from the upper portion of the semiconductor substrate, and a latch-up trigger current and is injected downwardly and sidewardly of the substrate from the wells of the first and second conductivity types is effectively absorbed, thus contributing to increasing the latch-up breakdown voltage. Further, a channel stop is formed in a self-aligned manner by the shallow well of a high concentration having the first conductivity type and the well of the second conductivity type formed beneath the insulation layer. Therefore, the production process is simplified and the distance is shortened very easily between the transistor of the first conductivity type and the transistor of the second conductivity type, thus making it possible to realize a complementary semiconductor device having a very high density.
Inventors
- 👤 Shinji Odanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:09
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10D84/854; H10W; H10W15/00; H10W15/01
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
213 words
A semiconductor device comprising: a semiconductor substrate of a first conduction type; a well which is of a second conduction type and which is selectively formed in the semiconductor substrate; a buried layer which is of the first conduction type, having a higher dopant concentration than the semiconductor substrate, which is formed in a deep region directly below the well which is of the second conduction type; and a well which is of the first conduction type, formed in a region which is more shallow than the buried layer and which extends in a plane surrounding the well which is of the second conduction type; wherein the well of the first conduction type and the buried layer are formed extending continuously within the semiconductor substrate, and have a high concentration of a dopant that is of the first conduction type at a position which is directly below an insulating isolation layer that is formed adjacent to a surface position of an edge of the well which is of the second conduction type, and with a transistor of the first conduction type being formed at the well which is of the second conduction type and a transistor of the second conduction type being formed at the well which is of the first conduction type.
Claim 2
Dependent Claim
213 words
A semiconductor device comprising: a semiconductor substrate of a first conduction type; a well which is of a second conduction type and which is selectively formed in the semiconductor substrate; a buried layer which is of the first conduction type, having a higher dopant concentration than the semiconductor substrate, which is formed in a deep region directly below the well which is of the second conduction type; and a well which is of the first conduction type, formed in a region which is more shallow than the buried layer and which extends in a plane surrounding the well which is of the second conduction type; wherein the well of the first conduction type and the buried layer are formed extending continuously within the semiconductor substrate, and have a high concentration of a dopant that is of the first conduction type at a position which is directly below an insulating isolation layer that is formed adjacent to a surface position of an edge of the well which is of the second conduction type, and with a transistor of the first conduction type being formed at the well which is of the second conduction type and a transistor of the second conduction type being formed at the well which is of the first conduction type.
Claim 3
Dependent Claim
78 words
A semiconductor device according to claim 1, in which a portion of the insulating isolation layer protrudes above the surface of the semiconductor substrate, and in which respective dopant profiles of the well which is of the first conduction type and the wekll which is of the second conduction type at a position directly below the insulating isolation layer are respectively more shallow than these respective dopant profiles at positions other than directly below the insulating isolation layer.
Claim 4
Dependent Claim
109 words
A semiconductor device according to claims 1 or 2, in which the highest concentration layer of the dopant profile of the well which is of the first conduction type is positioned in a low region of the substrate, while the highest concentration layer of the dopant profile of the well which is of the second conduction type is positioned in an upper region of the semiconductor substrate, and in which each of the transistors formed at the well which is of the first conduction type and the well which is of the second conduction type is formed in a region which is more shallow than the high concentration layers.
Claim 5
Dependent Claim
248 words
A semiconductor device comprising: a semiconductor substrate of a first conduction type; a well which is of a second conduction type and which is selectively formed in the semiconductor substrate; a buried layer which is of the first conduction type, having a higher dopant concentration than the semiconductor substrate, which is formed in a deep region directly below the well which is of the second conduction type; and a well which is of the first conduction type, formed in a region which is more shallow than the buried layer and which extends in a plane surrounding the well which is of the second conduction type; wherein the well of the first conduction type and the buried layer are formed extending continuously within the semiconductor substrate, and have a high concentration of a dopant that is of the first conduction type at a position which is directly below an insulating isolation layer that is formed adjacent to a surface position of an edge of the well which is of the second conduction type, with the maximum dopant concentration of the buried layer that is of the first conduction type being made greater than the maximum dopant concentration of the well that is of the first conduction type, and in which a transistor of the first conduction type is formed at the well which is of the second conduction type and a transistor of the second conduction type is formed at the well which is of the first conduction type.
Claim 6
Dependent Claim
248 words
A semiconductor device comprising: a semiconductor substrate of a first conduction type; a well which is of a second conduction type and which is selectively formed in the semiconductor substrate; a buried layer which is of the first conduction type, having a higher dopant concentration than the semiconductor substrate, which is formed in a deep region directly below the well which is of the second conduction type; and a well which is of the first conduction type, formed in a region which is more shallow than the buried layer and which extends in a plane surrounding the well which is of the second conduction type; wherein the well of the first conduction type and the buried layer are formed extending continuously within the semiconductor substrate, and have a high concentration of a dopant that is of the first conduction type at a position which is directly below an insulating isolation layer that is formed adjacent to a surface position of an edge of the well which is of the second conduction type, with the maximum dopant concentration of the buried layer that is of the first conduction type being made greater than the maximum dopant concentration of the well that is of the first conduction type, and in which a transistor of the first conduction type is formed at the well which is of the second conduction type and a transistor of the second conduction type is formed at the well which is of the first conduction type.
Claim 7
Dependent Claim
22 words
A semiconductor device according to claim 4, in which a portion of the insulating isolation layer protrudes above the semiconductor substrate surface.
Claim 8
Dependent Claim
111 words
A semiconductor device according to claim 4 or 5, in which the highest concentration layer of the dopant profile of the well which is of the first conduction type is positioned in a low region of the substrate, while the highest concentration layer of the dopant profile of the well which is of the second conduction type is positioned in an upper region of the semiconductor substrate, and in which each of the transistors that are formed at the well which is of the first conduction type and the well which is of the second conduction type is formed in a region which is more shallow than the high concentration layers.
Claim 9
Independent Claim
79 words
A method of manufacturing a semiconductor device, comprising: a pattern processing step of selectively forming a photoresist pattern on a semiconductor substrate; and executing implantation of ions of a first conduction type using the photoresist pattern to thereby simultaneously form regions of the first conduction type within a lower area of the substrate, where the substrate is not coated with the photoresist pattern, and an upper areas of the substrate where the substrate is coated with the photoresist pattern.
Claim 10
Independent Claim
79 words
A method of manufacturing a semiconductor device, comprising: a pattern processing step of selectively forming a photoresist pattern on a semiconductor substrate; and executing implantation of ions of a first conduction type using the photoresist pattern to thereby simultaneously form regions of the first conduction type within a lower area of the substrate, where the substrate is not coated with the photoresist pattern, and an upper areas of the substrate where the substrate is coated with the photoresist pattern.
Claim 11
Dependent Claim
20 words
A method of manufacturing a semiconductor device according to claim 7, in which edge portions of the photoresist are tapered.
Claim 12
Dependent Claim
39 words
A method of manufacturing a semiconductor device according to claim 8, in which the implantation is executed using an acceleration voltage in the range 100 KeV to 4 MeV for implantation of the ions of the first conduction type.
Claim 13
Independent Claim
82 words
A method of manufacturing a semiconductor device whereby, of a first and second film having respectively different values of ion implantation stopping power, the first film is formed over the entirity of a semiconductor substrate and the second film is selectively formed over the substrate, as an implantation pattern forming step, and whereby thereafter ion implantation is executed of ions of the first conduction type and ions of a second conduction type, followed by complete removal of the first and second films.
Claim 14
Independent Claim
82 words
A method of manufacturing a semiconductor device whereby, of a first and second film having respectively different values of ion implantation stopping power, the first film is formed over the entirity of a semiconductor substrate and the second film is selectively formed over the substrate, as an implantation pattern forming step, and whereby thereafter ion implantation is executed of ions of the first conduction type and ions of a second conduction type, followed by complete removal of the first and second films.
Claim 15
Dependent Claim
121 words
A method of manufacturing a semiconductor device according to claim 10, in which as a result of the implantation of the ions of the first conduction type, a region of the first conduction type is formed in an upper area of the semiconductor substrate where the substrate has been coated by the second film, and in a lower area of the substrate other than where the substrate has been coated by the second film, and furthermore whereby as a result of the implantation of the ions of the second conduction type, a region which is of the second conduction type is formed in an upper area within the semiconductor substrate, where the substrate has not been coated with the second film.
Claim 16
Dependent Claim
62 words
A method of manufacturing a semiconductor device according to claim 10 or 11, in which the implantation of ions of the first conduction type is executed using an acceleration voltage in the range 100 KeV to 4 MeV, and the implantation of ions of the second conduction type is executed using an acceleration voltage in the range 240 KeV to 7.2 MeV.
Claim 17
Independent Claim
125 words
A method of manufacturing a semiconductor device comprising: a pattern step of selectively forming a photoresist pattern upon a semiconductor substrate; and executing implantation of ions which are of a first conduction type and ions of a second conduction type, using the photoresist pattern; thereby forming a region which is of the second conduction type in an upper area within the semiconductor substrate, where the substrate is not coated with the photoresist pattern and, as a result of implantation of the ions which are of the first conduction type, forming a region which is of the first conduction type below the region which is of the second conduction type, within an upper area of the substrate where the substrate is coated with the photoresist pattern.
Claim 18
Independent Claim
125 words
A method of manufacturing a semiconductor device comprising: a pattern step of selectively forming a photoresist pattern upon a semiconductor substrate; and executing implantation of ions which are of a first conduction type and ions of a second conduction type, using the photoresist pattern; thereby forming a region which is of the second conduction type in an upper area within the semiconductor substrate, where the substrate is not coated with the photoresist pattern and, as a result of implantation of the ions which are of the first conduction type, forming a region which is of the first conduction type below the region which is of the second conduction type, within an upper area of the substrate where the substrate is coated with the photoresist pattern.
Claim 19
Dependent Claim
60 words
A method of manufacturing a semiconductor device according to claim 12, in which the implantation of ions of the first conduction type is executed using an acceleration voltage in the range 100 KeV to 4 MeV, and the implantation of ions of the second conduction type is executed using an acceleration voltage in the range 240 KeV to 7.2 MeV.
Claim 20
Independent Claim
205 words
A method of manufacturing a semiconductor device, comprising: an isolation step of selectively forming an insulating isolation layer upon a semiconductor substrate; a pattern step of selectively forming a photoresist pattern over the semiconductor substrate, including a part of the insulating isolation layer; and a step of executing implantation of ions of a first conduction type and ions of a second conduction type using the photoresist pattern, thereby forming a region which is of the second conduction type in an upper area within the semiconductor substrate, where the substrate is not covered by the photoresist pattern, and, as a result of implantation of the ions of the first conduction type, forming a region which is of the first conduction type within an area of the substrate which is below the region that is of the second conduction type and a region which is of the first conduction type in an upper area of the semiconductor substrate where the substrate is not covered by the photoresist pattern, and in which the regions which are of the first conduction type are formed as a continuous region, which extends immediately below the insulating isolation layer and which has a higher dopant concentration than that of the semiconductor substrate.
Claim 21
Independent Claim
205 words
A method of manufacturing a semiconductor device, comprising: an isolation step of selectively forming an insulating isolation layer upon a semiconductor substrate; a pattern step of selectively forming a photoresist pattern over the semiconductor substrate, including a part of the insulating isolation layer; and a step of executing implantation of ions of a first conduction type and ions of a second conduction type using the photoresist pattern, thereby forming a region which is of the second conduction type in an upper area within the semiconductor substrate, where the substrate is not covered by the photoresist pattern, and, as a result of implantation of the ions of the first conduction type, forming a region which is of the first conduction type within an area of the substrate which is below the region that is of the second conduction type and a region which is of the first conduction type in an upper area of the semiconductor substrate where the substrate is not covered by the photoresist pattern, and in which the regions which are of the first conduction type are formed as a continuous region, which extends immediately below the insulating isolation layer and which has a higher dopant concentration than that of the semiconductor substrate.
Claim 22
Dependent Claim
24 words
A method of manufacturing a semiconductor device according to claim 15, in which the isolation step further includes thermal processing of the semiconductor substrate.
Claim 23
Dependent Claim
23 words
A method of manufacturing a semiconductor device according to claim 15, in which the isolation step further comprises deposition of an insulating material.
Claim 24
Dependent Claim
64 words
A method of manufacturing a semiconductor device according to claim 15, 16 or 17, in in which the implantation of ions of the first conduction type is executed using an acceleration voltage in the range 100 KeV to 4 MeV, and the implantation of ions of the second conduction type is executed using an acceleration voltage in the range 240 KeV to 7.2 MeV.
Claim 25
Independent Claim
242 words
A method of manufacturing a semiconductor device comprising: a pattern step of selectively forming a photoresist pattern upon a semiconductor substrate; a step of implantation of ions which are of a first conduction type and ions of a second conduction type, using the photoresist pattern thereby forming a region which is of the second conduction type in an upper area within the semiconductor substrate, where the substrate is not coated with the photoresist pattern and, as a result of implantation of the ions which are of the first conduction type, forming a region which is of the first conduction type below the region which is of the second conduction type, within an upper area of the substrate where the substrate is coated with the photoresist pattern, and in which the regions in the upper and lower areas of the substrate which are of the first conduction type are formed as a continuous region, which extends immediately below an edge portion of the photoresist pattern and which has a higher dopant concentration than that of the semiconductor substrate; a photoresist removal step of removing the photoresist pattern; and an insulation isolation step of forming an insulating isolation layer which is positioned substantially centrally at a border between a region which is of the first conduction type and a region which is of the second conduction type which have been formed in an upper part of the semiconductor substrate by the ion implantation step.
Claim 26
Independent Claim
242 words
A method of manufacturing a semiconductor device comprising: a pattern step of selectively forming a photoresist pattern upon a semiconductor substrate; a step of implantation of ions which are of a first conduction type and ions of a second conduction type, using the photoresist pattern thereby forming a region which is of the second conduction type in an upper area within the semiconductor substrate, where the substrate is not coated with the photoresist pattern and, as a result of implantation of the ions which are of the first conduction type, forming a region which is of the first conduction type below the region which is of the second conduction type, within an upper area of the substrate where the substrate is coated with the photoresist pattern, and in which the regions in the upper and lower areas of the substrate which are of the first conduction type are formed as a continuous region, which extends immediately below an edge portion of the photoresist pattern and which has a higher dopant concentration than that of the semiconductor substrate; a photoresist removal step of removing the photoresist pattern; and an insulation isolation step of forming an insulating isolation layer which is positioned substantially centrally at a border between a region which is of the first conduction type and a region which is of the second conduction type which have been formed in an upper part of the semiconductor substrate by the ion implantation step.
Claim 27
Dependent Claim
23 words
A method of manufacturing a semiconductor device according to claim 19, in which the insulation isolation step comprises depostion of an insulating material.
Claim 28
Dependent Claim
60 words
A method of manufacturing a semiconductor device according to claim 19, in which the implantation of ions of the first conduction type is executed using an acceleration voltage in the range 100 KeV to 4 MeV, and the implantation of ions of the second conduction type is executed using an acceleration voltage in the range 240 KeV to 7.2 MeV.
References Cited (Backward Citations)
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