EP0336598A2
Expired / Lapsed
EP
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Arrangement for switching concentrated telecommunications packet traffic
Assignee: AT&T Inc
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Filing: 1989-03-21
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Granted: —
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Expires: 2009-03-21
Abstract
Abstract A high capacity metropolitan area network (MAN) is described. Data traffic from users is connected to data concentrators at the edge of the network, and is transmitted over fiber optic data links to a hub where the data is switched. The hub includes a plurality of data switching modules, each having a control means, and each connected to a distributed control space division switch. Advantageously, the data switching modules, whose inputs are connected to the concentrators, perform all checking and routing functions, while the 1024x1024 maximum size space division switch, whose outputs are connected to the concentrators, provides a large fan-out distribution network for reaching many concentrators from each data switching module. Distributed control of the space division switch permits several million connection and disconnection actions to be performed each second, while the pipelined and parallel operation within the control means permits each of the 256 switching modules to process at least 50,000 transactions per second. The data switching modules chain groups of incoming packets destined for a common outlet of the space division switch so that only one connection in that switch is required for transmitting each group of chained packets from a data switching module to a concentrator. MAN provides security features including a port identification supplied by the data concentrators, and a check that each packet is from an authorized source user, transmitting on a port associated with that user, to an authorized destination user that is in the same group (virtual network) as the source user. The data switching modules each use a synchronous data ring for transporting data packets between data link handlers and a plurality of memory access controllers and their associated memory modules.
Inventors
- 👤 Jayant Gurudatta Hemmady
- 👤 Michael Jeremy Knudsen
- 👤 William Paul Lidinsky
- 👤 Robert Kells Nichols
- 👤 Gaylord Warner Richards
- 👤 Gary Arthur Roediger
- 👤 Scott Blair Steele
- 👤 Ronald Clare Weddige
- 👤 Bruce Ronald Zelle
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 20:07
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
134 words
A data distribution means for switching data packets from a plurality of inputs to a plurality of outputs connectable to another switching network, comprising: memory control means for concurrently loading data from each of said plurality of inputs to a memory and unloading data from said memory to each of said plurality of outputs; and processing means; wherein said memory control means loads said memory in parallel from said plurality of inputs and unloads said memory in parallel to said plurality of outputs; wherein said processing means comprises means for chaining groups of data packets addressed to a common output of said another switching network; and wherein said processing means comprises means for controlling unloading of each of said groups of chained data packets in one sequence to one of said plurality of outputs.
Claim 2
Dependent Claim
134 words
A data distribution means for switching data packets from a plurality of inputs to a plurality of outputs connectable to another switching network, comprising: memory control means for concurrently loading data from each of said plurality of inputs to a memory and unloading data from said memory to each of said plurality of outputs; and processing means; wherein said memory control means loads said memory in parallel from said plurality of inputs and unloads said memory in parallel to said plurality of outputs; wherein said processing means comprises means for chaining groups of data packets addressed to a common output of said another switching network; and wherein said processing means comprises means for controlling unloading of each of said groups of chained data packets in one sequence to one of said plurality of outputs.
Claim 3
Dependent Claim
89 words
Apparatus of claim 1, wherein said another switching network is a circuit switching means for setting up circuit connections, and wherein said processing means further comprises: means for requesting a connection in said circuit switching means from an output of said data distribution means to an output of said circuit switching means; and means for controlling transmission of a chained group of data packets from said memory to said output of said data distribution for connection through said circuit switching means to said output of said circuit switching means.
Claim 4
Dependent Claim
31 words
Apparatus of claim 1 wherein said processing means further comprises means for checking on the authorization of transmission of each data packet to a destination specified by said each data packet.
Claim 5
Dependent Claim
165 words
A high-speed data distribution module for switching data packets from a plurality of inputs to a plurality of outputs, comprising: a plurality of memory modules; a plurality of first data link handlers each for accepting inputs from one of said plurality of inputs; a plurality of second data link handlers for transmitting data each to one of said plurality of outputs; a data transmission ring for transmitting data from ones of said first plurality of link handlers to said plurality of memory modules and for transmitting data from said plurality of memory modules to ones of said second plurality of data link handlers; a central control connected to said plurality of first data link handlers and said plurality of second data link handlers for allocating memory for data received by said first data link handlers for the storage of received data and for controlling transmission of said received data from said plurality of memory modules to ones of said second plurality of data link handlers.
Claim 6
Dependent Claim
165 words
A high-speed data distribution module for switching data packets from a plurality of inputs to a plurality of outputs, comprising: a plurality of memory modules; a plurality of first data link handlers each for accepting inputs from one of said plurality of inputs; a plurality of second data link handlers for transmitting data each to one of said plurality of outputs; a data transmission ring for transmitting data from ones of said first plurality of link handlers to said plurality of memory modules and for transmitting data from said plurality of memory modules to ones of said second plurality of data link handlers; a central control connected to said plurality of first data link handlers and said plurality of second data link handlers for allocating memory for data received by said first data link handlers for the storage of received data and for controlling transmission of said received data from said plurality of memory modules to ones of said second plurality of data link handlers.
Claim 7
Dependent Claim
65 words
Apparatus of claim 4 wherein said apparatus is connectable to a circuit switch and wherein said central control is further controlled by a program to request connections in said circuit switch, and to chain packets, destined for a common output of said circuit switch, for transmission as one sequence of packets from one of said second plurality of data link handlers to said circuit switch.
Claim 8
Dependent Claim
119 words
Apparatus of claim 5 wherein said data packets comprise header information identifying a source end user and source end user port number, a group number, and a destination end user wherein said central control comprises: means for checking that said source end user, said source end user port and said group number represent a combination authorized to transmit packets; means for ascertaining that said destination end user and said group represents a destination authorized to receive packets from said network and to identify a port for receiving data packets for said destination end user, and means responsive to a login request for accessing a data base system to verify whether a user transmitting said login request shall be authorized.
Claim 9
Dependent Claim
56 words
In a data switching means, a method of processing data packets comprising the steps of: storing each received data packet concurrently in a plurality of memory modules: chaining groups of data packets having a common destination; and unloading, concurrently from said plurality of memory modules, and in sequence, each of the packets of each chained group.
Claim 10
Dependent Claim
56 words
In a data switching means, a method of processing data packets comprising the steps of: storing each received data packet concurrently in a plurality of memory modules: chaining groups of data packets having a common destination; and unloading, concurrently from said plurality of memory modules, and in sequence, each of the packets of each chained group.
Claim 11
Dependent Claim
121 words
In a data network having a plurality of inlets and outlets comprising data switching means for switching received data packets, each packet comprising destination information, from at least one input to at least one output, a control means comprising: a plurality of first processors for controlling the storing of each of said received data packets in a memory means; and a plurality of second processors, responsive to said destination information of said received data packets, for ascertaining an identity of an outlet for reaching a destination specified by said destination information of each data packet, and for chaining, for each outlet of said network, memory locations in said memory means of data packets whose destinations are reachable via said each outlet.
Claim 12
Dependent Claim
121 words
In a data network having a plurality of inlets and outlets comprising data switching means for switching received data packets, each packet comprising destination information, from at least one input to at least one output, a control means comprising: a plurality of first processors for controlling the storing of each of said received data packets in a memory means; and a plurality of second processors, responsive to said destination information of said received data packets, for ascertaining an identity of an outlet for reaching a destination specified by said destination information of each data packet, and for chaining, for each outlet of said network, memory locations in said memory means of data packets whose destinations are reachable via said each outlet.
Claim 13
Dependent Claim
38 words
The control means of claim 8 further comprising means for requesting connection by a switching network, connected to said outlets, from one of said at least one output of said data switching means to one of said outlets.
Claim 14
Dependent Claim
44 words
The control means of claim 8, wherein each of said packets further comprises source information, wherein said second plurality of processors comprises at least one processor for verifying authority of a source, identified by said source information of a packet, to transmit said packet.
Claim 15
Dependent Claim
44 words
The control means of claim 10 wherein each of said packets comprises an identity of a port transmitting said packet, wherein said at least one processor for verifying authorization of a source further comprises means for verifying said authorization by checking said port identity.
Claim 16
Dependent Claim
18 words
The control means of claim 11 wherein said second processors comprise means for chaining packets in first-in-first-out order.
Claim 17
Dependent Claim
183 words
A control means for a data switching module of a data network comprising: a plurality of first processors for storing received data packets in memory; a memory manager processor for allocating to said first processors addresses in memory where said packets are to be stored; a plurality of second processors for communicating with said first processors, including receiving from said first processors header data of said received data packets and transmitting to said first processors memory addresses allocated by said memory manager; a memory distributor processor for communicating said addresses allocated by said memory manager to said second processors; a plurality of source checker processors responsive to said header data received from said second processors for checking in data of tables of said source checker processors, that a source name comprised in said header data has been authorized to transmit data over said network; a plurality of routing processors for determining a destination for each of said packets; wherein said memory manager processor is responsive to signals from said plurality of third processors to release memory for distribution by said memory distributor processor.
Claim 18
Dependent Claim
183 words
A control means for a data switching module of a data network comprising: a plurality of first processors for storing received data packets in memory; a memory manager processor for allocating to said first processors addresses in memory where said packets are to be stored; a plurality of second processors for communicating with said first processors, including receiving from said first processors header data of said received data packets and transmitting to said first processors memory addresses allocated by said memory manager; a memory distributor processor for communicating said addresses allocated by said memory manager to said second processors; a plurality of source checker processors responsive to said header data received from said second processors for checking in data of tables of said source checker processors, that a source name comprised in said header data has been authorized to transmit data over said network; a plurality of routing processors for determining a destination for each of said packets; wherein said memory manager processor is responsive to signals from said plurality of third processors to release memory for distribution by said memory distributor processor.
Claim 19
Dependent Claim
168 words
The control means of claim 13 further comprising: a queue manager processor for chaining packets to be transmitted to each data transmission facility accessible via a circuit switch to said data switching module; a plurality of third processors for controlling the transmission of data packets stored in said memory to said circuit switch; a switch setup control processor, connectable to said circuit switch, responsive to signals from said queue manager processor for requesting connections in said switch; and a plurality of fourth processors responsive to signals from said source checker processors for communicating with a data base to receive authorization data and for distributing such authorization data to said source checker processors and said router processors; wherein said switch setup control processor is responsive to signals from said switch to cause one of said plurality of third processors to transmit data to said switch; wherein said switch setup control processor is responsive to output signals from said plurality of third processors for requesting a disconnection by said switch.
Claim 20
Dependent Claim
80 words
The control means of claim 14, further comprising: an operation, administration and maintenance monitor processor means, responsive to signals from said plurality of fourth processors for accessing said data base; wherein said source checker processors check for authorization of a combination of a source port, source name and group number comprised in said header data; wherein said routing processors check that a combination of a destination name and group number comprised in said header data is authorized to receive packets.
Claim 21
Dependent Claim
39 words
In a data switching means, a method of processing received data packets comprising the steps of: storing said received data packets; determining a destination for each stored data packet; and chaining groups of data packets having a common destination.
Claim 22
Dependent Claim
39 words
In a data switching means, a method of processing received data packets comprising the steps of: storing said received data packets; determining a destination for each stored data packet; and chaining groups of data packets having a common destination.
Claim 23
Independent Claim
84 words
A method of communicating between a plurality of memory modules each having a memory controller and at least one data link controller over a synchronous data ring, comprising the steps of: assigning to each pairing, of memory controller and data link controller, at least one time slot of said synchronous data ring interconnecting said memory controllers and said at least one data link controller, and transmitting data between a memory controller and a data link controller on the time slot assigned for that pair.
Claim 24
Independent Claim
84 words
A method of communicating between a plurality of memory modules each having a memory controller and at least one data link controller over a synchronous data ring, comprising the steps of: assigning to each pairing, of memory controller and data link controller, at least one time slot of said synchronous data ring interconnecting said memory controllers and said at least one data link controller, and transmitting data between a memory controller and a data link controller on the time slot assigned for that pair.
Claim 25
Dependent Claim
35 words
The method of claim 17 further comprising the step of: initializing said memory controller with an address and a count of number of words to be transmitted from storage in memory starting with said address.
Claim 26
Dependent Claim
22 words
The method of claim 18 wherein said initializing comprises transmitting a control word from said data link controller to said memory controller.
Claim 27
Dependent Claim
44 words
The method of claim 17 wherein a single time slot is assigned for transmitting data from one of said data link controllers to one of said memory controllers, and for transmitting data from said one memory controller to one of said data link controllers.
Claim 28
Dependent Claim
237 words
Apparatus for communicating between a plurality of input data link handlers, a plurality of memory modules, and a plurality of output data link handlers, comprising: a synchronous data ring having one time slot for each pairing of an input data link controller and a memory module, said time slot also being used for communicating between that memory module and an output data link controller, and a plurality of time slots for sending control signals from each of said plurality of input data link controllers and said plurality of output data link controllers to all memory modules; each of said memory modules comprising a direct memory access unit for taking data from said synchronous ring for storing in a memory array of an associated memory module and for reading data from said memory array of said associated memory module to said synchronous data ring; wherein each of said plurality of input data link controllers sends a control address to all of said direct memory access units for storing data received from said each data link controller in said associated memory array at an address starting with said control address; and wherein each of said plurality of output data link controllers sends another control word to all of said direct memory access units for reading data from said memory array for delivery by said synchronous data ring to an output data link controller that sent said other control word.
Claim 29
Dependent Claim
237 words
Apparatus for communicating between a plurality of input data link handlers, a plurality of memory modules, and a plurality of output data link handlers, comprising: a synchronous data ring having one time slot for each pairing of an input data link controller and a memory module, said time slot also being used for communicating between that memory module and an output data link controller, and a plurality of time slots for sending control signals from each of said plurality of input data link controllers and said plurality of output data link controllers to all memory modules; each of said memory modules comprising a direct memory access unit for taking data from said synchronous ring for storing in a memory array of an associated memory module and for reading data from said memory array of said associated memory module to said synchronous data ring; wherein each of said plurality of input data link controllers sends a control address to all of said direct memory access units for storing data received from said each data link controller in said associated memory array at an address starting with said control address; and wherein each of said plurality of output data link controllers sends another control word to all of said direct memory access units for reading data from said memory array for delivery by said synchronous data ring to an output data link controller that sent said other control word.
Claim 30
Dependent Claim
44 words
The apparatus of claim 21 further comprising a central control means for supplying addresses to said data link controllers, wherein said central control means has access to said synchronous data ring in a time slot for accessing data in any of said memory modules.
Claim 31
Dependent Claim
98 words
Apparatus for communicating data between a plurality of memory modules and at least one data link controller, comprising: a plurality of memory access controllers each for controlling one of said memory modules; and a synchronous data ring interconnecting said at least one data link controller and said plurality of memory access controllers; each pairing of one of said memory access controllers and one of said at least one data link controllers being assigned one time slot of a repetitive time frame for the transmission of data between said one data link controller and said one memory access controller.
Claim 32
Dependent Claim
98 words
Apparatus for communicating data between a plurality of memory modules and at least one data link controller, comprising: a plurality of memory access controllers each for controlling one of said memory modules; and a synchronous data ring interconnecting said at least one data link controller and said plurality of memory access controllers; each pairing of one of said memory access controllers and one of said at least one data link controllers being assigned one time slot of a repetitive time frame for the transmission of data between said one data link controller and said one memory access controller.
References Cited (Backward Citations)
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