Semiconductor device having a structure which makes parasitic transistors hard to operate and method of manufacture thereof

Claim 1

A semiconductor device comprising: a semiconductor substrate ( 1 ) having a region (2) of one conductivity type on a major surface thereof; a first base region (14; 24) of opposite conduc­tivity type formed selectively within said region (2) of one conductivity type; a second base region (15; 25) of opposite conduc­tivity type formed selectively within said first base region (14; 24) and having a higher impurity concent­ration than that of said first base region (14; 24); a source region ( 16 ) of one conductivity type formed across and within said first and second base regions (14; 24 and 15; 25); and a gate electrode (9) opposed to a channel region (7) with a gate insulating (8) layer interposed there­between, said channel region (7) being a portion of said first base region (14; 24) that is sandwiched between said region (2) of one conductivity type and said source region ( 16 ) and exposed to the major surface of said semiconductor substrate ( 1 ), characterized in that said source region ( 16 ) has a lightly doped region (16a; 26a) and a heavily doped region (16b; 26b); and that said heavily doped region (16b; 26b) of said source region ( 16 ) is entirely formed within said second base region (15; 25).

Claim 11

A method of manufacturing a semiconductor device, comprising the steps of: forming a region (2) of one conductivity type on a major surface of a semiconductor substrate ( 1 ); depositing a polysilicon layer over said region (2) of one conductivity type with an insulating layer inter­posed therebetween and forming a gate insulating layer (8) and a gate electrode (9) by selective etching; forming a first base region (14; 24) of opposite conductivity type within said region (2) of one conduc­tivity type by diffusing impurities; forming an opening for the subsequent formation of a second base region (15; 25) of opposite conductivity type within said first base region (14; 24) and dif­fusing impurities through said opening to form said second base region (15; 25) of opposite conductivity type, said second base region (15; 25) having a higher impurity concentration than that of said first base region (14; 24) and a smaller depth than that of said first base region (14; 24); forming a source region ( 16 ) of one conductivity type across said first and second base region (14; 24 and 15; 25) by diffusing impurities; and forming a source electrode (11) to cover said gate electrode (9) with an interlayer insulating layer (10) interposed therebetween and to make ohmic contact with said source region ( 16 ) and said second base region (15; 25), characterized in that said source region ( 16 ) has a lightly doped source region (16a; 26a) and a heavily doped source region (16b; 26b), and that the step of forming said source region ( 16 ) includes the steps of: forming said heavily doped source region (16b; 26b) within said second base region (15; 25) by diffusing impurities, said heavily doped source region (16b; 26b) being entirely formed within said second base region (15; 25); and forming said lightly doped source region (16a; 26a) within said first base region (14; 24) by diffusing impurities.

Claim 12

A method of manufacturing a semiconductor device, comprising the steps of: forming a region (2) of one conductivity type on a major surface of a semiconductor substrate ( 1 ); depositing a polysilicon layer over said region (2) of one conductivity type with an insulating layer inter­posed therebetween and forming a gate insulating layer (8) and a gate electrode (9) by selective etching; forming a first base region (14; 24) of opposite conductivity type within said region (2) of one conduc­tivity type by diffusing impurities; forming an opening for the subsequent formation of a second base region (15; 25) of opposite conductivity type within said first base region (14; 24) and dif­fusing impurities through said opening to form said second base region (15; 25) of opposite conductivity type, said second base region (15; 25) having a higher impurity concentration than that of said first base region (14; 24) and a smaller depth than that of said first base region (14; 24); forming a source region ( 16 ) of one conductivity type across said first and second base region (14; 24 and 15; 25) by diffusing impurities; and forming a source electrode (11) to cover said gate electrode (9) with an interlayer insulating layer (10) interposed therebetween and to make ohmic contact with said source region ( 16 ) and said second base region (15; 25), characterized in that said source region ( 16 ) has a lightly doped source region (16a; 26a) and a heavily doped source region (16b; 26b), and that the step of forming said source region ( 16 ) includes the steps of: forming said heavily doped source region (16b; 26b) within said second base region (15; 25) by diffusing impurities, said heavily doped source region (16b; 26b) being entirely formed within said second base region (15; 25); and forming said lightly doped source region (16a; 26a) within said first base region (14; 24) by diffusing impurities.