Processor-processor synchronization

Claim 2

Method of synchronizing two asynchronously operating processing units (1,2), said synchronization being performed by one of the processors (1 or 2) by means of a branch instruction and tests for a busy and exceptional state of the other processor (2 or 1), characterized in that when synchronism is required said one processor (1 or 2) issues a single branch on pattern (BPT) instruction by which in combination a conditional branch is made to perform a first test on a specific condition (e.g. result available) of the other processor (2 or 1), which causes said one processor to wait until said condition is met, after said condition is met a second test is made on an exceptional status (e.g. overflow) which might be caused in said other processor during its operation, and if the second test results in a non-exceptional status, said one processor proceed with its next sequential instructions (NSI), but when an exceptional status is detected, said one processor branches to a sub-routine which is provided for handling said exceptional status.

Claim 3

Method of claim 1, characterized in that for performing a branch on pattern (BPT) instruction the present address in said one processor's (1 or 2) addressing means (21,26,30), the present instruction in its instruction register (22) and the present instruction cycle in its instruction cycle means (24,25,29) are blocked until the other processor (2 or 1) has arrived at said specific condition (e.g. result available), if an exceptional status is not detected the said blocked components are de-blocked so that the next sequential instruction (NSI) can be processed, but when an exceptional status is detected the said blocked components are de-blocked and a branch address (BA) which is the address of the first instruction of the exception handling sub-routine is sent to the said addressing means so that the first instruction of the said sub-routine can be performed.

Claim 4

Method of claim 1 and/or 2, characterized in that said branch on pattern instruction (BPT) carries in its instruction format the patterns which are tested on.

Claim 5

Arrangement for carrying out the method of claims 1, 2 and/or 3, characterized in that in the one processor (1 or 2) additional OR-gates (33,34,35) are provided which are used to increase the number of the hold inputs of the addressing means (21,26,30), the instruction register (22) and the instruction cycle means (24,25,29), said hold inputs being known per se, to allow the passage of hold signals (HOLD) generated by an additional AND-gate (32) when the operation decoder (23) has identified a branch on pattern (BPT) instruction (signal on line BPTL) in said instruction register and at the same time the other processor (2 or 1) is busy (signal CPB on line 11), whereby the address in the said address means, the instruction in the said instruction - register and the instruction cycle in the said instruction cycle means are held and a further AND-gate (31) is provided in the one processor (1 or 2) which generates a control signal (S-BR) for the said addressing means when a signal (EXH) indicating an exceptional status of the other processor and simultaneously a signal indicating a branch on pattern instruction in the said instruction register are present so that a branch address (BA) can be sent from the said operation decoder to said addressing means via said AND-gate and a control gate (30), being part of said addressing means.