Multilayer printed-circuit board comprising surface-mounted memories

Claim 2

A multilayer printed circuit board comprising: a plurality of integrated circuit packages, each having a plurality of input pins for receiving a corresponding number of signals; a multilayer printed circuit board comprising a top layer, a bottom layer and a number of intermediate layers, said top and bottom layers having repetitive patterns of pads which are mirror images of each other, each of said pad patterns including pads for plated through holes contained in said circuit board with a predetermined spacing between the centers of said holes; a plurality of conductors of minimum length connecting predetermined ones of said pads to said plated through hole pads on said top and bottom layers of said board so that a plurality of said plated through holes are shared between corresponding integrated circuit packages mounted on said top and bottom layers; and said plurality of said integrated circuit packages being mounted on other ones of said pads on said top and bottom layers of said board in a paired fashion for enabling an exchange of input pin signal assignments based upon an operational characteristic of the devices included in said packages so as to reduce the number of said pads for plated through holes.

Claim 3

The board of claim 1 wherein said devices are high density DRAM integrated circuits.

Claim 4

The board of claim 2 wherein each of said DRAM integrated circuits have a storage capacity of 1 megabits x 1 bit.

Claim 5

The board of claim 1 wherein a plurality of said input signals are address signals and said operational characteristic of said devices is the ability to scramble the order of said address signals applied to said input pins without interferring with the normal operation of said devices.

Claim 6

The board of claim 1 wherein a substantially equal number of said plated through holes in said board are distributed in rows so as to simplify internal connections.

Claim 7

The board of claim 5 wherein said rows of holes are separated by a predetermined spacing selected to permit the use of standard test equipment.

Claim 8

The board of claim 6 wherein said predetermined spacing is one hundredths of an inch from center to center.

Claim 9

The board of claim 1 wherein said board is of multilayer construction and said plurality of integrated circuit packages are mounted on said board using surface mount construction.

Claim 10

The board of claim 1 wherein said repetitive pattern of pads is repeated to provide a spacing for facilitating access to check for defects.

Claim 11

A multilayer printed circuit board comprising: a plurality of integrated circuit packages for housing a corresponding number of high density storage devices, each having a plurality of input pins for receiving a corresponding number of signals; a multilayer printed circuit board comprising a top layer surface and a bottom layer surface, said top and bottom layer surfaces having repetitive patterns of pads which are mirror images of each other, each of said pad patterns including pads for mounting said integrated circuit packages and pads associated with plated through holes contained in said circuit board with a predetermined spacing between the centers of said holes; a plurality of wiring conductors connecting predetermined ones of said pads to said plated through hole pads on said top and bottom layer surfaces of said board so that a plurality of said plated through holes are shared between corresponding integrated circuit packages mounted on said top and bottom layer surfaces; and said plurality of said integrated circuit packages being mounted on said mounting pads on said top and bottom layer surfaces of said board in a paired fashion for enabling an exchange of input pin signal assignments based upon a predetermined operational characteristic of said storage devices so as to reduce to a minimum the number of said pads associated with said plated through holes.

Claim 12

A multilayer printed circuit board comprising: a plurality of integrated circuit packages for housing a corresponding number of high density storage devices, each having a plurality of input pins for receiving a corresponding number of signals; a multilayer printed circuit board comprising a top layer surface and a bottom layer surface, said top and bottom layer surfaces having repetitive patterns of pads which are mirror images of each other, each of said pad patterns including pads for mounting said integrated circuit packages and pads associated with plated through holes contained in said circuit board with a predetermined spacing between the centers of said holes; a plurality of wiring conductors connecting predetermined ones of said pads to said plated through hole pads on said top and bottom layer surfaces of said board so that a plurality of said plated through holes are shared between corresponding integrated circuit packages mounted on said top and bottom layer surfaces; and said plurality of said integrated circuit packages being mounted on said mounting pads on said top and bottom layer surfaces of said board in a paired fashion for enabling an exchange of input pin signal assignments based upon a predetermined operational characteristic of said storage devices so as to reduce to a minimum the number of said pads associated with said plated through holes.

Claim 13

The board of claim 10 wherein said devices are high density DRAM integrated circuits.

Claim 14

The board of claim 11 wherein each of said DRAM integrated circuits have a storage capacity of 1 megabits x 1 bit.

Claim 15

The board of claim 10 wherein a plurality of said input signals are address signals and said operational characteristic of said devices is the ability to scramble the order of said address signals applied to said input pins without interferring with the normal operation of said devices.

Claim 16

The board of claim 10 wherein a substantially equal number of said plated through holes included in said board are distributed in rows so as to simplify internal connections.

Claim 17

The board of claim 14 wherein said rows of holes are separated by a predetermined spacing selected to permit the use of standard test equipment.

Claim 18

The board of claim 15 wherein said predetermined spacing is one hundredths of an inch from center to center.

Claim 19

The board of claim 10 wherein said board is of multilayer construction and said plurality of integrated circuit packages are mounted on said surfaces of said board using surface mount construction.

Claim 20

The board of claim 10 wherein said repetitive pattern of pads is repeated to provide a predetermined spacing between successive repetitive patterns for facilitating access to check for defects.

Claim 23

The board of claim 19 wherein said devices are high density DRAM integrated circuits, each having a storage capacity of 1 megabits x 1 bit.

Claim 24

The method of claim 19 further including the step of scrambling said input signal connections corresponding to predetermined ones of address signal assignments in a manner which minimizes said number of pads associated with said holes.

Claim 25

The memory of claim 19 wherein said method further includes the step of: distributing said groups of holes in rows having substantially equal numbers of holes in said board so as to simplify internal connections.

Claim 26

The method of claim 22 wherein said method further includes the step of: separating said rows of holes by a predetermined amount of spacing to permit the use of standard test equipment.

Claim 27

The method of claim 19 wherein said method further includes the step of: repeating said pattern of pads at pretermined intervals for facilitating access to check for defects.

Claim 28

The method of claim 19 wherein said method further includes the step of: soldering said pins of said plurality of integrated circuit packages to said pads using surface mount technology.