EP0334627A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Multiprocessor architecture
Assignee: 3DLabs Ltd
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Filing: 1989-03-22
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Granted: —
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Expires: 2009-03-22
Abstract
Abstract A numeric processing subsystem, where at least three processors concurrently run separate processes. One of the three is a control processor (110), one is a data transfer processor (120), which controls the external interface, and one or several are numeric processors (130). Preferably this subsystem also includes at least a megabyte of cache memory (140), which is linked to the floating-point processor by a very high-bandwidth bus. The interface to the numeric processor(s) is so constrained that a variety of integrated circuits can be readily substituted. To compensate for the different pin-out and routing requirements of different chips, exchangeable subboards are preferably used to mount the arithmetic chips. To achieve this chip-independence without sacrificing speed, an extremely flexible and highly multiported register file is used at the interface from the cache memory (140) to the numeric processing subsystem. To achieve algorithm flexibility, parallel writes from data cache memory to the control storage of the numeric processing subsystem are preferably possible. At least one of the numeric processors is preferably a floating-point processors, and one or more others may be application-customized processors. The application-customized processor is especially well adapted for some particular class of operations, such as discrete Fourier transform operations, and the numeric processor provides acceptably high speed on the general range of numeric computations. The data transfer processor (120) controls several external interfaces, including a port, for configuring multiple subsystems together, which includes two high-bandwidth input ports and a high-bandwidth output port. This permits a wide variety of highly pipelined and/or parallel architectures to be readily implemented.
Inventors
- 👤 David Robert Baldwin
- 👤 Osman Kent
- 👤 Yavuz Ahishalilar
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 11:23
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F9/3879; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8061; G06F15/8069
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
143 words
A processing system, comprising: a control processor , which contains sequencing logic connected to retrieve microcoded instructions sequentially, and arithmetic logic, connected to execute at least some portions of said microcoded instructions retrieved by said sequencing logic; a numeric processor , operable concurrently and asynchronously with said control processor, which executes instructions from a respective control store; wherein said control processor controls writing to said control store of said numeric processor; and wherein some fields of said microcoded instructions retrieved by said sequencing logic of said control processor, including fields which control said arithmetic logic, are stored in a first control store which is closely integrated with said arithmetic logic, and other fields of said microcoded instructions, including fields which control data access to said numeric processor, are stored in a second control store which is more closely integrated with said numberic processor.
Claim 2
Dependent Claim
143 words
A processing system, comprising: a control processor , which contains sequencing logic connected to retrieve microcoded instructions sequentially, and arithmetic logic, connected to execute at least some portions of said microcoded instructions retrieved by said sequencing logic; a numeric processor , operable concurrently and asynchronously with said control processor, which executes instructions from a respective control store; wherein said control processor controls writing to said control store of said numeric processor; and wherein some fields of said microcoded instructions retrieved by said sequencing logic of said control processor, including fields which control said arithmetic logic, are stored in a first control store which is closely integrated with said arithmetic logic, and other fields of said microcoded instructions, including fields which control data access to said numeric processor, are stored in a second control store which is more closely integrated with said numberic processor.
Claim 3
Dependent Claim
59 words
The system of Claim 1, further comprising at least one application-customized processor, which runs faster than said numeric processor at a predetermined class of operations, but which does not run faster than said numeric processor at numeric operations generally; wherein said control processor can selectively command said numeric processor and said application-customized processor to execute a respective instruction sequence.
Claim 4
Dependent Claim
68 words
The system of Claim 1 or 2, further comprising: a plurality of external data interfaces, including at least a first data interface, which can access main memory over a system bus, and also a second data interface, which includes at least two high-bandwidth input ports and one high-bandwidth output port; and a data transfer processor, which controls external interface controllers, and which runs concurrently with said control processor.
Claim 5
Dependent Claim
50 words
The system of Claim 3, further comprising a plurality of other systems according to Claim 3, linked together in a data flow structure having a predetermined degree of pipelining and/or parallelism, by at least two local data busses, said data busses linking respective ports of respective second data interfaces together.
Claim 6
Dependent Claim
44 words
The system of Claim 4, further comprising a host computer, connected to provide high-level instructions to at least one of said subsystems over a first bus, wherein at least one of said systems can also access a main memory bank over said first bus.
Claim 7
Independent Claim
37 words
The system of any preceding claim, wherein said second control store of said control processor is more closely integrated with said control store of said numeric processor than with said first control store of said control processor.
Claim 8
Independent Claim
46 words
The system of any preceding claim, wherein said second control store of said control processor and said control store of said numeric processor are both included in a common circuit board, and said first control store of said control processor is included in a different subboard.
Claim 9
Independent Claim
55 words
The system of any preceding claim, further comprising at least two said numeric processors, which are each operable asynchronously with said control processor and said data transfer processor; and wherein each of said numeric processors is separately enabled to read or write when an address in said cache memory is accessed by said control processor.
Claim 10
Dependent Claim
21 words
The subsystem of Claim 8, wherein said control processor is operable to command said numeric processors to execute respective instruction sequences.
Claim 11
Dependent Claim
52 words
The subsystem of Claim 8 or 9, wherein said control processor can address commands to any selected one of said numeric processors or to some but not all possible groups of said processors, using an address word which has fewer bits than the number of independently addressable ones of said numeric processors.
Claim 12
Dependent Claim
133 words
A processing system comprising: a numeric processor , and a control processor connected to command said numeric processor to execute an instruction sequence, said control and numeric processors being concurrently operable asynchronously, and said numeric processor including internal numeric processing components which operate at a faster rate than the maximum speed of said control processor; and a data cache memory ; wherein said numeric processor interfaces to said data cache memory through a multiport register file having a first port , which provides a data interface to said data cache memory and is clocked in partial synchrony with said control processor, and at least one other port , which provides a data interface to said internal numeric processing components and is clocked in synchrony with at least one said internal numeric processing component.
Claim 13
Dependent Claim
133 words
A processing system comprising: a numeric processor , and a control processor connected to command said numeric processor to execute an instruction sequence, said control and numeric processors being concurrently operable asynchronously, and said numeric processor including internal numeric processing components which operate at a faster rate than the maximum speed of said control processor; and a data cache memory ; wherein said numeric processor interfaces to said data cache memory through a multiport register file having a first port , which provides a data interface to said data cache memory and is clocked in partial synchrony with said control processor, and at least one other port , which provides a data interface to said internal numeric processing components and is clocked in synchrony with at least one said internal numeric processing component.
Claim 14
Dependent Claim
86 words
The processing system of Claim 11, wherein said numeric processor includes a multiplier, and wherein said numeric processor interfaces to said data cache memory through interface logic and said multiport register file, and wherein said interface logic interfaces directly to said data cache memory and operates substantially asynchronously with said data cache memory, and wherein said first port of said register file provides a data interface directly to said interface logic, and said other port of said register file provides a data interface to said multiplier.
Claim 15
Dependent Claim
93 words
The system of Claim 11 or 12, wherein said other port of said register file comprises: a second port and a third port , which are connected to selectably provide parallel data outputs from said register file to first and second one of said internal numeric processing components; a fourth port , which is connected to selectably receive outputs of said internal numeric processing components; and a fifth port , comprising an input port which selectably reads previously enabled outputs from said register file back into a desired location of said register file.
Claim 16
Dependent Claim
60 words
The processing system of Claim 13, wherein said fourth port of said register file is connected to a local results bus to selectably receive outputs of said internal numeric processing components, and wherein said numeric processor further comprises a local stack, comprising a memory and an address controller, which is connected to read from and write to said results bus.
Claim 17
Dependent Claim
61 words
The processing system of Claim 13, wherein said fourth port of said register file is connected to a local results bus to selectably receive outputs of said internal numeric processing components, and wherein said numeric processor further comprises a table memory, comprising a memory and an address controller, which is connected to provide data-dependent address outputs onto said local results bus.
Claim 18
Dependent Claim
28 words
A method of performing histogram calculations in a system according to Claim 15, wherein histogram inputs are collected in said table memory iteratively as said calculations are performed.
Claim 19
Independent Claim
60 words
The system of any preceding claim, wherein said fourth port of said register file is connected to a local results bus to selectably receive outputs of said internal numeric processing components, and wherein said second and third ports of said register file are respectively connected to first and second operand busses, and are separately latchable and have separate enable controls.
Claim 20
Dependent Claim
94 words
The system of Claim 11, wherein said first port of said register file is connected to said cache memory through a bank of holding registers , and wherein said cache memory and said holding registers are configured to be multiple words wide, and wherein transfers between said holding registers and said register file are clocked by a transfer clock which provides pulses at approximately the clock frequency of said internal numeric processing components, gated so that bursts of said pulses begin only at times which are synchronized to clock pulses of said control processor.
Claim 21
Dependent Claim
36 words
The system of Claim 18, wherein said transfer clock is controllable to mask individual pulses of said bursts, whereby subsets of the words in said holding registers are selectable for transfer into said multiport register file.
Claim 22
Dependent Claim
109 words
The system of Claim 11, wherein said cache memory is interfaced to said multiport register file through a bank of holding registers and a cache bus , connected so that said multiport register file appears to said holding registers to be two words wide, and appears to said arithmetic calculation units to be only one word wide; and wherein said cache bus has at least four times as many data lines as the standard word length of said internal numeric processing components; and further comprising transfer logic , connected to selectably multiplex the data in said holding registers down onto pairs of two words in said fast register file.
Claim 23
Dependent Claim
24 words
The system of Claim 20, further comprising means for replicating words of data when transferring data from said register file to said holding registers.
Claim 24
Dependent Claim
57 words
The system of Claim 20 or 21, further comprising means for inserting data-valid bits of unused fields of said register file, connected so that, when a single word is desired to be written into said first port of said register file, a pair of words is written in, and one word is flagged with a data-valid bit.
References Cited (Backward Citations)
No citation records indexed.
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