Dynamic RAM

Claim 1

A dynamic RAM comprising: a semiconductor substrate; a plurality of semiconductor pillar projections separated by grooves formed in longitudinal and trans­verse directions in said semiconductor substrate, said semiconductor pillar projections being arranged in a matrix manner; a plurality of MOS capacitors formed on side sur­faces at a lower portion of each of said semiconductor pillar projections, said each MOS capacitor including a memory node formed in side surface at the lower portion of each semiconductor pillar projection, a capacitor insulating film formed on the side surface at the lower portion of each semiconductor pillar projection, and a capacitor electrode formed on said capacitor insulating film; a plurality of MOSFETS formed on side surfaces at an upper portion of each semiconductor pillar projec­tion, said each MOSFET including a channel region formed at least on the side surface at the upper portion of each semiconductor pillar projection, source and drain regions formed above and below said channel region to sandwich said channel region, a gate insulating film formed on the side sur­face at the upper portion of each semiconductor pillar projection in which said channel region is formed, and a gate electrode formed on said gate insu­lating film; and a bit line connected to an upper surface of each semiconductor pillar projections, said bit line being in contact with an upper end face of each semiconductor pillar projection in a self-alignment manner.

Claim 5

A method for manufacturing a dynamic RAM, comprising the steps of: selectively forming a first mask including an anti-­oxidation film on a semiconductor substrate; anisotropically etching said semiconductor substrate by using said first mask to form first grooves in longitudinal and transverse directions in said semi­conductor substrate, thereby forming a plurality of semiconductor pillar projections; forming a second mask including an anti-oxidation film on side surfaces of each of said semiconductor pillar projections; anisotropically etching said semiconductor substrate by using said first and second masks as anti-­etching masks to form second grooves in said first grooves; forming a diffusion layer serving as a memory node in side surfaces at a lower portion of each semiconduc­tor pillar projections by using said first and second masks as anti-diffusion masks; forming an element isolation layer on bottom por­tions of said second grooves; forming a capacitor insulating film on the side surfaces at the lower portion of each semiconductor pillar projections; burying a capacitor electrode in said second grooves; covering a surface of said capacitor electrode with a first insulating film; removing said second mask to form a gate electrode on the side surfaces at an upper portion of each semi­conductor pillar projections with a gate insulating film interposed therebetween; covering a region except for said first mask with a second insulating film including a material different from that of said first mask; removing said first mask to expose an upper end face of each semiconductor pillar projections; forming a diffusion layer serving as one of a source and a drain in the exposed upper end face of each semiconductor pillar projections; and forming and patterning a conductor film to form a bit line to be connected to said diffusion layer.

Claim 6

A method for manufacturing a dynamic RAM, comprising the steps of: selectively forming a first mask including an anti-­oxidation film on a semiconductor substrate; anisotropically etching said semiconductor substrate by using said first mask to form first grooves in longitudinal and transverse directions in said semi­conductor substrate, thereby forming a plurality of semiconductor pillar projections; forming a second mask including an anti-oxidation film on side surfaces of each of said semiconductor pillar projections; anisotropically etching said semiconductor substrate by using said first and second masks as anti-­etching masks to form second grooves in said first grooves; forming a diffusion layer serving as a memory node in side surfaces at a lower portion of each semiconduc­tor pillar projections by using said first and second masks as anti-diffusion masks; forming an element isolation layer on bottom por­tions of said second grooves; forming a capacitor insulating film on the side surfaces at the lower portion of each semiconductor pillar projections; burying a capacitor electrode in said second grooves; covering a surface of said capacitor electrode with a first insulating film; removing said second mask to form a gate electrode on the side surfaces at an upper portion of each semi­conductor pillar projections with a gate insulating film interposed therebetween; covering a region except for said first mask with a second insulating film including a material different from that of said first mask; removing said first mask to expose an upper end face of each semiconductor pillar projections; forming a diffusion layer serving as one of a source and a drain in the exposed upper end face of each semiconductor pillar projections; and forming and patterning a conductor film to form a bit line to be connected to said diffusion layer.

Claim 7

A method for manufacturing a dynamic RAM, comprising the steps of: selectively forming a first mask including an anti-­oxidation film on a semiconductor substrate; anisotropically etching said semiconductor substrate by using said first mask to form first grooves in longitudinal and transverse directions in said semi­conductor substrate, thereby forming a plurality of semiconductor pillar projections; forming a second mask including an anti-oxidation film on side surfaces of each of said semiconductor pillar projections; anisotropically etching said semiconductor substrate by using said first and second masks as anti-­etching masks to form second grooves in said first grooves; forming a diffusion layer serving as a memory node in side surfaces at a lower portion of each semiconduc­tor pillar projections by using said first and second masks as anti-diffusion masks; forming a third mask on the side surfaces of each semiconductor pillar projections including said second mask; anisotropically etching said second grooves using said third mask as an anti-etching mask to form third grooves in said second grooves; forming a diffusion layer for element isolation in bottom portions of said third grooves; removing said third masks; forming a capacitor insulating film on the side surfaces at the lower portion of each semiconductor pillar projections while said second mask remains; burying a capacitor electrode in said second grooves; covering a surface of said capacitor electrode with a first insulating film; removing said second mask and forming a gate electrode on side surfaces at an upper portion of each semiconductor pillar projections with a gate insulating film interposed therebetween; covering a region except for said first mask with a second insulating film including a material different from that of said first mask; removing said first mask to expose an upper end face of each semiconductor pillar projections; forming a diffusion layer serving as one of a source and a drain in the exposed upper end face of each semiconductor pillar projections; and forming and patterning a conductor film to form a bit line to be connected to said diffusion layer.

Claim 8

A method for manufacturing a dynamic RAM, comprising the steps of: selectively forming a first mask including an anti-­oxidation film on a semiconductor substrate; anisotropically etching said semiconductor substrate by using said first mask to form first grooves in longitudinal and transverse directions in said semi­conductor substrate, thereby forming a plurality of semiconductor pillar projections; forming a second mask including an anti-oxidation film on side surfaces of each of said semiconductor pillar projections; anisotropically etching said semiconductor substrate by using said first and second masks as anti-­etching masks to form second grooves in said first grooves; forming a diffusion layer serving as a memory node in side surfaces at a lower portion of each semiconduc­tor pillar projections by using said first and second masks as anti-diffusion masks; forming a third mask on the side surfaces of each semiconductor pillar projections including said second mask; anisotropically etching said second grooves using said third mask as an anti-etching mask to form third grooves in said second grooves; forming a diffusion layer for element isolation in bottom portions of said third grooves; removing said third masks; forming a capacitor insulating film on the side surfaces at the lower portion of each semiconductor pillar projections while said second mask remains; burying a capacitor electrode in said second grooves; covering a surface of said capacitor electrode with a first insulating film; removing said second mask and forming a gate electrode on side surfaces at an upper portion of each semiconductor pillar projections with a gate insulating film interposed therebetween; covering a region except for said first mask with a second insulating film including a material different from that of said first mask; removing said first mask to expose an upper end face of each semiconductor pillar projections; forming a diffusion layer serving as one of a source and a drain in the exposed upper end face of each semiconductor pillar projections; and forming and patterning a conductor film to form a bit line to be connected to said diffusion layer.

Claim 9

A method for manufacturing a dynamic RAM, comprising the steps of: selectively forming a first mask including an anti-­oxidation film on a semiconductor substrate; anisotropically etching said semiconductor substrate by using said first mask to form first grooves in longitudinal and transverse directions in said semiconductor substrate, thereby forming a plurality of semiconductor pillar projections; forming a second mask including an anti-oxidation film on side surfaces of each of said semiconductor pillar projections; anisotropically etching said semiconductor substrate by using said first and second masks as anti-­etching masks to form second grooves in said first grooves; forming a diffusion layer serving as a memory node in side surfaces at a lower portion of each semiconduc­tor pillar projections by using said first and second masks as anti-diffusion masks; forming an element isolation layer in bottom por­tions of said second grooves; forming a capacitor insulating film on the side surfaces at the lower portion of each semiconductor pillar projections; burying a capacitor electrode in said second grooves; covering a surface of said capacitor electrode with a first insulating film; removing said second mask and forming a gate electrode on side surfaces at an upper portion of each semiconductor pillar projections with a gate insulating film interposed therebetween; covering an entire surface of said semiconductor substrate, in which said gate electrodes are formed, with a second insulating film to flatten a semiconductor structure; etching said second insulating film to expose said first mask; selectively etching and removing said exposed first mask to expose an upper end face of each semiconductor pillar projections; forming a diffusion layer serving as one of a source and a drain in the exposed upper end face; and forming and patterning a conductor film to form a bit line to be connected to said diffusion layer.

Claim 10

A method for manufacturing a dynamic RAM, comprising the steps of: selectively forming a first mask including an anti-­oxidation film on a semiconductor substrate; anisotropically etching said semiconductor substrate by using said first mask to form first grooves in longitudinal and transverse directions in said semiconductor substrate, thereby forming a plurality of semiconductor pillar projections; forming a second mask including an anti-oxidation film on side surfaces of each of said semiconductor pillar projections; anisotropically etching said semiconductor substrate by using said first and second masks as anti-­etching masks to form second grooves in said first grooves; forming a diffusion layer serving as a memory node in side surfaces at a lower portion of each semiconduc­tor pillar projections by using said first and second masks as anti-diffusion masks; forming an element isolation layer in bottom por­tions of said second grooves; forming a capacitor insulating film on the side surfaces at the lower portion of each semiconductor pillar projections; burying a capacitor electrode in said second grooves; covering a surface of said capacitor electrode with a first insulating film; removing said second mask and forming a gate electrode on side surfaces at an upper portion of each semiconductor pillar projections with a gate insulating film interposed therebetween; covering an entire surface of said semiconductor substrate, in which said gate electrodes are formed, with a second insulating film to flatten a semiconductor structure; etching said second insulating film to expose said first mask; selectively etching and removing said exposed first mask to expose an upper end face of each semiconductor pillar projections; forming a diffusion layer serving as one of a source and a drain in the exposed upper end face; and forming and patterning a conductor film to form a bit line to be connected to said diffusion layer.

Claim 19

A method for manufacturing a dynamic RAM, comprising the steps of: preparing first and second substrates each having an insulating film thereon; bringing a first insulating film of said first substrate into contact with a second insulating film of said second substrate, and bonding said first and second insulating films by a wafer bonding technique, thereby forming a bonded wafer; performing anisotropic etching from a first substrate side by using said bonded wafer as a starting material and said first and second insulating films as etching stoppers, thereby forming grooves in longitudi­nal and transverse directions in said first substrate to define a plurality of semiconductor pillar projections separated by said grooves; forming a MOS capacitor and a MOSFET at lower and upper portions, respectively, of each of said semicon­ductor pillar projections; and connecting a bit line to one of a source and a drain of said MOSFET.

Claim 20

A method for manufacturing a dynamic RAM, comprising the steps of: preparing first and second substrates each having an insulating film thereon; bringing a first insulating film of said first substrate into contact with a second insulating film of said second substrate, and bonding said first and second insulating films by a wafer bonding technique, thereby forming a bonded wafer; performing anisotropic etching from a first substrate side by using said bonded wafer as a starting material and said first and second insulating films as etching stoppers, thereby forming grooves in longitudi­nal and transverse directions in said first substrate to define a plurality of semiconductor pillar projections separated by said grooves; forming a MOS capacitor and a MOSFET at lower and upper portions, respectively, of each of said semicon­ductor pillar projections; and connecting a bit line to one of a source and a drain of said MOSFET.

Claim 26

A method for manufacturing a dynamic RAM, comprising the steps of: selectively forming a first mask including an insu­lating film on a surface of a semiconductor substrate; etching said semiconductor substrate by using said first mask to form grooves in longitudinal and trans­verse directions, thereby defining a plurality of semiconductor pillar projections separated by said grooves; forming a MOS capacitor and a MOSFET at lower and upper portions, respectively, of each of said semicon­ductor pillar projections; dividing said semiconductor pillar projections into a plurality of blocks, and forming a word line contact region on at least selected one of said semiconductor pillar projections in each of said blocks with an insu­lating layer interposed therebetween, said dividing step including the substeps of causing said first mask used to form said grooves to remain on said selected semiconductor pillar projection, forming a second mask on said selected semi­conductor pillar projection before forming a gate electrode of said MOSFET on side surface at the upper portion of each semiconductor pillar projection in a self-alignment manner, and forming said gate electrode by using said second mask, and causing a gate electrode material to remain on said first mask on said selected semiconductor pillar projection to form said word line contact region; connecting some of said gate electrodes of said MOSFET constituting memory cells to said word line con­tact region via contact holes; and connecting a bit line to one of a source and a drain of said MOSFET.

Claim 27

A method for manufacturing a dynamic RAM, comprising the steps of: selectively forming a first mask including an insu­lating film on a surface of a semiconductor substrate; etching said semiconductor substrate by using said first mask to form grooves in longitudinal and trans­verse directions, thereby defining a plurality of semiconductor pillar projections separated by said grooves; forming a MOS capacitor and a MOSFET at lower and upper portions, respectively, of each of said semicon­ductor pillar projections; dividing said semiconductor pillar projections into a plurality of blocks, and forming a word line contact region on at least selected one of said semiconductor pillar projections in each of said blocks with an insu­lating layer interposed therebetween, said dividing step including the substeps of causing said first mask used to form said grooves to remain on said selected semiconductor pillar projection, forming a second mask on said selected semi­conductor pillar projection before forming a gate electrode of said MOSFET on side surface at the upper portion of each semiconductor pillar projection in a self-alignment manner, and forming said gate electrode by using said second mask, and causing a gate electrode material to remain on said first mask on said selected semiconductor pillar projection to form said word line contact region; connecting some of said gate electrodes of said MOSFET constituting memory cells to said word line con­tact region via contact holes; and connecting a bit line to one of a source and a drain of said MOSFET.