Microprocessor interface circuits

Claim 2

In an integrated circuit (12) providing connection to at least a first (10) and a second (14) type of microprocessor generating a first and a second timing signal, interface means responsive to said first and second timing signals for detecting which said type of microprocessor is connected to said integrated circuit and for generating a read data and a write data signal therefrom.

Claim 3

An integrated circuit having interface means according to claim 1, said interface means comprising: detection means (26, 36, 38) responsive to said first and second timing signals for generating a first and a second type signal indicative of the microprocessor connected to said integrated circuit; logic means (28, 32, 34, 42) responsive to said first and second timing signals and said first and said second type signals for generating said read data and said write data signals.

Claim 4

An integrated circuit having interface means according to claim 2 wherein said detection means is further responsive to a reset signal, wherein said detection means comprises: a NAND gate (26) receiving at a first complemented input said first timing signal, at a second complemented input said second timing signal, and at a first true input said reset signals generating therefrom at an output terminal a third timing signals; and flip-flop means (36, 38) responsive to said third timing signal and said reset signal, for generating said first and second type signals.

Claim 5

In an integrated circuit having interface means according to claim 3 wherein flip-flop means comprises: a second NAND gate (36) receiving at a first input said reset signal and having a second input terminal and generating said second type signal therefrom at an output terminal; and a third NAND gate (38) receiving at a first input said third timing signal and having a second input terminal connected to said second NAND gate output terminal and generating said first type signal thereform at an output terminal, said output terminal connected to said second input terminal of said second NAND gate.

Claim 6

In an integrated circuit having interface means according to claim 2, wherein said logic means comprises: a first AND gate (28) receiving at a true input said second timing signal, and at a complemented input said first timing signal and generating said read data signal thereform; a second AND gate (32) receiving at a first complemented input said first type signal and at a second complemented input said second timing signal and generating an output signal therefrom; a third AND gate (34) receiving at a first complemented input said second type signal, at a second complemented input said first timing signal and at a third input said second timing signal and generating an output signal therefrom; a first OR gate (42) receiving said output signals generated by said second and third AND gates and generating said write data signal therefrom.