§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
EP0332911A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Local memory fast selecting apparatus

Assignee: Bull HN Information Systems Italia SpA
•
Filing: 1989-02-25
•
Granted: —
•
Expires: 2009-02-25
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Local memory fast selection apparatus in a data processing system having a plurality of memory resources and addressing by logical/virtual addresses which are converted into physical addresses, comprising a memory management unit MMU (2) for converting a logical address in a physical address and for generating a destination code which identifies the memory resource, an auxiliary memory (16) having the same number of addressable locations of the MMU (2) and loaded together with the MMU (2), this last with a physical address corresponding to the logical address by which the MMU (2) is addressed and with a destination code, the auxiliary memory (16) with a bit decoded from said destination code for selecting a predetermined memory resource, the auxiliary memory (16) and the MMU (2) being read out together with the same logical address, so as to jointly obtain a physical address from the MMU (2) and a selection signal of the predetermined memory resource from the auxiliary memory (16), without any delay caused by decoding operations.

Inventors

  • 👤 Tiziano Maccianti
  • 👤 Angelo Oldani

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 05:27
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0284

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 176 words
1) Local memory fast selection apparatus, in a data processing system having a plurality of memory resources and addressing by logic/virtual addresses which are converted into physical addresses, comprising a memory management unit MMU for converting a logical address into a physical address and for generating a destination code which identifies the memory resource to be selected in said plurality, a decoder connected to outputs of said MMU for receiving said destination code and for outputing a local memory selection signal, an auxiliary memory addressed by the same logical address used to address said MMU and having an input connected to an output of said decoder for receiving said local memory selection signal and for storing a bit corresponding to said selection signal when said MMU and said auxiliary memory are jointly controlled for a write operation, said auxiliary memory having an output connected to said local memory for outputing to said local memory, when controlled for a read operation jointly with said MMU, a selection signal corresponding to the stored bit, without any decoding delay.
Claim 2
Dependent Claim 176 words
1) Local memory fast selection apparatus, in a data processing system having a plurality of memory resources and addressing by logic/virtual addresses which are converted into physical addresses, comprising a memory management unit MMU for converting a logical address into a physical address and for generating a destination code which identifies the memory resource to be selected in said plurality, a decoder connected to outputs of said MMU for receiving said destination code and for outputing a local memory selection signal, an auxiliary memory addressed by the same logical address used to address said MMU and having an input connected to an output of said decoder for receiving said local memory selection signal and for storing a bit corresponding to said selection signal when said MMU and said auxiliary memory are jointly controlled for a write operation, said auxiliary memory having an output connected to said local memory for outputing to said local memory, when controlled for a read operation jointly with said MMU, a selection signal corresponding to the stored bit, without any decoding delay.
Claim 3
Dependent Claim 31 words
2) Apparatus as claimed in Claim 1, wherein said auxiliary memory has said input distinct from said output, said output being directly connected to a selection input of said local memory.
Claim 4
Dependent Claim 62 words
3) Apparatus as claimed in claim 1 wherein said auxiliary memory has said input common to said output, said input being connected to an output of said decoder through a gate enabled by a write command for said MMU, said output being connected to a selection input of said local memory through a gate disabled by a write command for said MMU.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag