EEPROM having a data controlled erasing and writing mode

Claim 2

Integrated memory circuit comprising: - an electrically erasable programmable non-volatile memory having memory locations arranged in rows and columns; - programming means for under control of data at a memory data input programming a selected memory location; - erasing means for erasing a selected memory location under control of data supplied at the memory data input, the data having a predetermined logical value; characterized, in that : - the programming means comprises for each individual column a respective first voltage generating means having a first data input for in dependence on data at the first data input, in a first manner applying a high voltage to the selected memory location in the relevant column; - the erasing means comprises for each individual column a respective second voltage generating means having a second data input for in dependence on data at said second data input having the predetermined logical value, in a second manner applying the high voltage to a selected memory location in the relevant column; the first and second voltage generating means associated to the individual column being alternatively controllable by the data simultaneously fed to the associated first and second data input.

Claim 3

Integrated memory circuit as claimed in Claim 1, wherein the first and the second voltage generating means of a plurality of columns are addressable simultaneously be respective data simultaneously fed to the respective first and respective second data inputs.

Claim 4

Integrated memory circuit as claimed in Claim 1 or 2, wherein the first voltage generating means comprises a latch means coupled to said first data input.

Claim 5

Integrated memory circuit as claimed in Claim 1 or 2, wherein the first voltage generating means comprises a latch means coupled to said first data input and wherein the second voltage generating means comprises a logic gate means having a gate input coupled to said second data input and having a gate output coupled to a further latch means.

Claim 6

Integrated memory circuit as claimed in Claim 3 or 4, wherein each latch means is coupled to a data bus via a column selection gate.

Claim 7

Integrated memory circuit as claimed in Claim 1, wherein each memory location comprises B bit cells, B ≧ 1, each bit cell comprising a series arrangement of a conduction channel of a programmable transistor having a floating gate and of a conduction channel of a selection transistor, the series arrangement being disposed between a bit line and a supply line, wherein the selection transistors of memory locations of a same row have control electrodes connected to a word line, each individual memory location having an individual activation line connected to control electrodes of the programmable transistors in said indidivual memory location, there being associated with each individual memory location a switch for connecting said activation line either to a supply voltage in a memory location program mode or to the high voltage in a memory location erase mode, said switch being controllable by the second voltage generating means associated to the particular column wherein said individual memory location is located, and wherein the first voltage generating means comprises B level shifters each coupled to a respective first data input terminal out of B first data input terminals constituting said first data input, each level shifter having control outputs connected to a respective supply line and a respective bit line for in the memory location erase mode feeding said lines with a supply voltage, the relevant word line carrying the high voltage, and for, in order to write a first logical value into the relevant bit cell, feeding the relevant bit line with the high voltage and keeping the relevant supply line floating, the relevant word line carrying the high voltage, and for, in order to write a second logical value into the relevant bit cell, feeding said lines with a supply voltage, the relevant word line carrying the high voltage.

Claim 8

Integrated memory circuit as claimed in Claim 6, wherein each level shifter comprises: a first current path comprising a conduction channel of a first transistor connected to the supply voltage and a conduction channel of a second transistor connected to the high voltage; a second current path comprising a conduction channel of a third transistor coupled to the supply voltage and a conduction channel of a fourth transistor connected to the high voltage, wherein a first node between the first and second transistor is connected to a control electrode of the fourth transistor and wherein a second node between the third and fourth transistor is connected to a control electrode of the second transistor; control electrodes of the first and third transistor being coupled to the relevant first data input terminal so as to be mutually oppositewise controlled by a data bit at said relevant first data input terminal, a fifth transistor having a conduction channel disposed between the supply voltage and the relevant supply line and having a control electrode connected to the control electrode of the third transistor, the second node being connected to the relevant bit line, the first, third and fifth transistor being of a first conductivity type, the second and fourth transistor being of a second conductivity type.

Claim 9

Integrated memory circuit as claimed in Claim 7, wherein for each level shifter there is provided a latch having complementary latch outputs connected to the control electrodes of the first and the third transistor and having a latch input coupled to the relevant first data input terminal.

Claim 10

Integrated memory circuit as claimed in Claim 7, wherein each second voltage generating means comprises a further level shifter comprising: a third current path comprising a conduction channel of a sixth transistor connected to the supply voltage, and a conduction channel of a seventh transistor connected to the high voltage; a fourth current path comprising a conduction channel of an eighth transistor connected to the supply voltage and a conduction channel of a ninth transistor connected to the high voltage; wherein a third node between the sixth and seventh transistor is connected to a control electrode of the ninth transistor and wherein a fourth node between the eighth and ninth transistor is connected to a control electrode of the seventh transistor; the second voltage generating means further comprising a logic gate having a gate input connected to said second data input and having a gate output coupled to control electrodes of said sixth and eighth transistor so as to mutually oppositewise control said sixth and eighth transistor; the control electrode of said eighth transistor and said fourth node being connected to a first and second switch control line, respectively, that are connected to the switches of the memory locations in the relevant column; each switch comprising a first switch transistor, having a conduction channel disposed between the supply voltage and the activation line and having a control electrode connected to said first switch control line, and comprising a second switch transistor having a conduction channel disposed between the activation line and the relevant word line and having a control electrode connected to said second switch control line, said sixth transistor, eighth transistor, first switch transistor and second switch transistor being of the first conductivity type, the seventh and ninth transistor being of the second conductivity type.

Claim 11

Level shifter suitable for use in an integrated memory circuit as claimed in Claim 7.

Claim 12

Further level shifter suitable for use in an integrated memory circuit as claimed in Claim 9.