Circuitry for driving an electronically commutated DC motor

Abstract

Abstract In the case of known DC motors of this type having motor windings (w1 to w3) and a rigidly coupled position sensor (P), drive signals (GS1 to GS3) for cyclically driving power transistors (T1 to T3) are decoded from rotor position signals (HS1 to HS3). The signals are intended to be configured such that undesired winding voltage peaks are avoided. The power transistors (T1 to T3), configured as voltage-controlled field-effect transistors, in each case have a gate network allocated to them which is formed from a voltage divider (e.g. R1, R7) with a gate centre tap and located between the operating voltage and earth, and a further resistor (e.g. R4), connected to the centre tap. Analog comparators (N1 to N3) are provided as decoding devices, whose outputs are in each case connected to the centre tap via one of the output resistors (R4, R5 or R6). A reference voltage (VRef) is jointly supplied to the first comparator inputs and one of the position signals (HS1, HS2 or HS3) is supplied to each of the second inputs, which position signal is also applied to the centre tap of the gate network (e.g. R2, R8, R5) of the power transistor (e.g. T2) which is subsequently driven in the cyclic sequence. <IMAGE>

Inventors

• 👤 Josef Dipl.-Ing. Immler (Fh)

Bibliographic Details