IC card

Claim 2

An IC card (10) having a processor (1), first memory means (14) for storing a system program (41) of said processor, second memory means (13) for storing an application program (42), and third memory means (11, 12), comprised of a rewritable non-volatile memory or a volatile memory, for storing various kinds of process data whereby data is transmitted and received to and from an external apparatus, said IC card comprising inhibition address checker means (5) for deciding whether an accessing address issued from said processor is destined for an address value or an address range which should be inhibited from being accessed by the application program and producing an access inhibiting signal (8) when accessing is decided to be inhibited, program running signal generator means (7) for generating a program running signal (9) indicating that the application program is in operation, when the application program is started or the application program is under execution, and access inhibition means (6) for responding to the access inhibiting signal when the program running signal is present to inhibit said processor from accessing said second memory means or said third memory means.

Claim 3

An IC card according to Claim 1 wherein said inhibition address checher means holds an address value or address range which should not be accessed under the execution of the application program, said address value or address range being stored in any one of said first, second and third memory means.

Claim 4

An IC card according to Claim 1 wherein said inhibition address checker means holds an address value or address range which should be permitted to be accessed under the execution of the application program, said address value or address range being stored in any one of said first, second and third memory means.

Claim 5

An IC card according to any one of Claims 1 to 3 wherein said third memory means is a rewritable non-volatile memory, and at least two of said first, second and third memory means are allocated to divided areas of a single rewritable non-volatile memory.

Claim 6

An IC card (10) having a processor (1), a signal input/output unit (3) through which said processor transmits and receives data to and from an external apparatus, first memory means (14) for storing a first program (41) used to operate said processor, second memory means (13) for storing a second program (42) which is received by said processor from said external apparatus through said signal input/output unit under the instructions of said first program, and third memory means (11, 12) for storing process data processed by said processor and data necessary for normal operation of said processor whereby said processor is operable under the instructions of said second program stored in said second memory means, said IC card comprising inhibition address setting means (4) for setting an address value which should be inhibited from being accessed by said second program, and access inhibition means (6) for inhibiting said processor from accessing when under the operation of said second program an accessing address issued from said processor is destined for the address value which is set in said inhibition address setting means and which should be inhibited from being accessed by said second program.

Claim 7

An IC card (10) having a processor (1), a signal input/output unit (3) through which said processor transmits and receives data to and from an external apparatus, first memory means (14) for storing a first program (41) used to operate said processor, second memory means (13) for storing a second program (42) which is received by said processor from said external apparatus through said signal input/output unit under the instructions of said first program, and third memory means (11, 12) for storing process data processed by said processor and data necessary for normal operation of said processor whereby said processor is operable under the instructions of said second program stored in said second memory means, said IC card comprising inhibition address setting means (4) for setting an address value which should be inhibited from being accessed by said second program, and access inhibition means (6) for inhibiting said processor from accessing when under the operation of said second program an accessing address issued from said processor is destined for the address value which is set in said inhibition address setting means and which should be inhibited from being accessed by said second program.

Claim 8

An IC card according to Claim 5 wherein said third memory means is comprised of an internal register, a RAM and an EEPROM.

Claim 9

An IC card according to Claim 5 wherein said first memory means comprises a mask ROM.

Claim 10

An IC card according to Claim 6 wherein a first program storage area of said first memory means, a second program storate area of said second memory means and said internal register and RAM of said third memory means are allocated to an address space to which said processor is accessible.

Claim 11

An IC card according to Claim 5 wherein said first program is a system program for said processor and said second program is an application program for said processor.

Claim 12

An IC card according to Claim 9 wherein said first memory means comprises an EEPROM.

Claim 13

An IC card according to Claim 5 further comprising inhibition address checker means (5) for deciding whether the accessing address from said processor is the address value which is set in said inhibition address setting means and which should be inhibited from being accessed by said second program, and second program running detecting means (7) for detecting that said second program is in operation, said access inhibition means (6) being operable to inhibit said processor from accessing on the basis of results of decision by said inhibition address checker means and resuilts of detection by said second program running detecting means.

Claim 14

An IC card according to Claim 11 wherein said inhibition address checker means produces an access inhibiting signal (8) when deciding that the accessing address from said processor is the address value which is set in said inhibition address setting means and which should be inhibited from being accessed by said second program, said second program running detecting means produces a program running signal (6) when detecting that said second program is in operation, and said access inhibition means inhibits said processor from accessing when the access inhibiting signal and the program running signal are both present.