EP0330836A2
Expired / Lapsed
EP
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Method for multiprocessor system having self-allocating processors
Assignee: Convex Computer Corp
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Filing: 1989-01-25
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Granted: —
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Expires: 2009-01-25
Abstract
Abstract A computer system (20) comprises a plurality of independent processors (24,26) which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers (46) divided into a group of frames and a set of semaphores (48) which correspond respectively to the registers. Typical processes have both serial and parallel code segments. During serial execution, a process is executed by a single processor, but when a parallelization instruction is encountered, which indicates that code can be executed in parallel, a semaphore is posted to invite other processors to join in parallel execution of the process. If any other processors in the system are idle, those processors detect the semaphore and accept a thread of process operation. Two or more processors may join in parallel operation if sufficient operations are available. However, if all processors are busy, then the processor conducting the serial operation will also execute all of the parallel operations. Thus, the processors are self-allocated, rather than being used on a demand or master-servant basis. This permits a greater throughput for the system because processors are not held idle when there is available process work to be done.
Inventors
- 👤 David M. Chastain
- 👤 James E. Mankovich
- 👤 Gary B. Gostin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 14:04
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F15/173; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30076; G06F9/30087; G06F9/3009; G06F9/38; G06F9/3824; G06F9/3834; G06F9/46; G06F9/50; G06F9/5061; G06F9/5066; G06F9/52
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
254 words
A method for parallel execution of a process in a computer system having a plurality of processors, the method comprising the steps of: initiating execution of a process by writing process state parameters for said process into defined registers in a communications register set which is accessible to all of the processors in the system, commencing serial execution of the instruction code of said process by a first of said processors, upon execution of a parallelization instruction for said process by said first processor, which parallelization instruction indicates parallel process operations for said process which can be executed in parallel, (a) writing additional process state parameters for said process into said communication register set to allow other of said processors to join in the execution of said parallel process operations for said process, and (b) signalling to all other of said processors that said parallel process operations are available for execution by setting a semaphore register associated with said process state parameters, monitoring of said semaphore by one or more of said other processors, when said other processors are in an idle state, to detect when said first processor has posted said semaphore to request that other ones of said processors join in execution of said parallel process operations of said process, and upon detection of the setting of said semaphore by one or more of said other processors, accessing said process state parameters stored in said communication register set and commencing execution of said parallel process operations by said one or more processors.
Claim 2
Independent Claim
254 words
A method for parallel execution of a process in a computer system having a plurality of processors, the method comprising the steps of: initiating execution of a process by writing process state parameters for said process into defined registers in a communications register set which is accessible to all of the processors in the system, commencing serial execution of the instruction code of said process by a first of said processors, upon execution of a parallelization instruction for said process by said first processor, which parallelization instruction indicates parallel process operations for said process which can be executed in parallel, (a) writing additional process state parameters for said process into said communication register set to allow other of said processors to join in the execution of said parallel process operations for said process, and (b) signalling to all other of said processors that said parallel process operations are available for execution by setting a semaphore register associated with said process state parameters, monitoring of said semaphore by one or more of said other processors, when said other processors are in an idle state, to detect when said first processor has posted said semaphore to request that other ones of said processors join in execution of said parallel process operations of said process, and upon detection of the setting of said semaphore by one or more of said other processors, accessing said process state parameters stored in said communication register set and commencing execution of said parallel process operations by said one or more processors.
Claim 3
Dependent Claim
48 words
The method as recited in Claim 1 including the step of: all but one of said one or more processors, which have executed said parallel process operations, returning to an idle state and the remaining one of said one or more processors continuing serial execution of said process.
Claim 4
Dependent Claim
37 words
The method as recited in Claim 2 wherein the one of said processors which continues serial execution of said process is the last of said one or more processors to complete execution of said parallel process operations.
Claim 5
Dependent Claim
35 words
The method recited in Claim 1 wherein the step of initiating execution of a process is carried out by an operating system of the computer system, said operating system functioning in one of said processors.
Claim 6
Independent Claim
312 words
A method for parallel execution of a process in a computer system having a plurality of processors, the method comprising the steps of: serially executing said process in a first of said processors, said process having code that includes parallelization instructions which indicate process operations that can be executed in parallel, writing process state information for said process into a communication register set, setting a selected semaphore, which is associated with said communication register set, and writing additional process state information related to said process into said communication register set by said first processor upon execution of one of said parallelization instructions for requesting that other of said processors join in execution of selected process operations which can be executed in parallel, said additional process state information for at least partially defining said selected process operations, monitoring said semaphore by one or more of said processors when said processors are in an idle state to detect when said semaphore has been changed to said set state, initiating execution of one of said selected process operations, by use of said process state information stored in said communication register set, by one of said processors upon detection of said set semaphore by said one processor, initiating execution of another one of said selected process operations, by use of said process state information stored in said communication register set, by another of said processors upon detection of said set semaphore by said another processor, whereby at least two of said process operations are executed concurrently by said computer system, upon completion of the last of said selected process operations by a last one of said processors, clearing said semaphore by said last processor to indicate that there are no pending parallel process operations to be executed, and resuming serial execution of said process by one of said processors after completion of said selected process operations.
Claim 7
Independent Claim
312 words
A method for parallel execution of a process in a computer system having a plurality of processors, the method comprising the steps of: serially executing said process in a first of said processors, said process having code that includes parallelization instructions which indicate process operations that can be executed in parallel, writing process state information for said process into a communication register set, setting a selected semaphore, which is associated with said communication register set, and writing additional process state information related to said process into said communication register set by said first processor upon execution of one of said parallelization instructions for requesting that other of said processors join in execution of selected process operations which can be executed in parallel, said additional process state information for at least partially defining said selected process operations, monitoring said semaphore by one or more of said processors when said processors are in an idle state to detect when said semaphore has been changed to said set state, initiating execution of one of said selected process operations, by use of said process state information stored in said communication register set, by one of said processors upon detection of said set semaphore by said one processor, initiating execution of another one of said selected process operations, by use of said process state information stored in said communication register set, by another of said processors upon detection of said set semaphore by said another processor, whereby at least two of said process operations are executed concurrently by said computer system, upon completion of the last of said selected process operations by a last one of said processors, clearing said semaphore by said last processor to indicate that there are no pending parallel process operations to be executed, and resuming serial execution of said process by one of said processors after completion of said selected process operations.
Claim 8
Dependent Claim
34 words
The method as recited in Claim 5 wherein the step of writing process state information is performed by an operating system of said computer system, said operating system functioning in one of said processors.
Claim 9
Dependent Claim
288 words
A multi-processor computer system for parallel execution of a process, comprising: a plurality of communication register sets, each set comprising a plurality of communication registers, at least one respective semaphore register associated with one register in each of said communication register sets, a respective process-independent communication index register associated with each of said processors, each of said communication index registers for storing a communication index register value therein which is a first address segment for addressing one of the communication register sets, respective circuit means associated with each of said processors for selecting communication index register values independent of said process, wherein said process execution is independent of the one of said processors which is physically executing said process and said circuit means further for producing a second address segment which is derived from instructions in said process, said second address segment for addressing one of the registers in each of said communication register sets, bus circuitry connected to said communication registers, said communication index registers and said circuit means for conveying addresses and data associated with said communication registers, and means connected to said communication index registers, said circuit means and said bus circuitry for combining said first and second address segments to produce a composite address for one of said registers within said communication register sets, whereby one or more of said processors can communicate with a selected one of said communication register sets through said bus circuitry by use of said composite addresses for detecting a predetermined state for the semaphore register associated with said selected communication register set and said processors can obtain process state data from said selected communication register set for executing said process concurrently in more than one of said processors.
Claim 10
Dependent Claim
288 words
A multi-processor computer system for parallel execution of a process, comprising: a plurality of communication register sets, each set comprising a plurality of communication registers, at least one respective semaphore register associated with one register in each of said communication register sets, a respective process-independent communication index register associated with each of said processors, each of said communication index registers for storing a communication index register value therein which is a first address segment for addressing one of the communication register sets, respective circuit means associated with each of said processors for selecting communication index register values independent of said process, wherein said process execution is independent of the one of said processors which is physically executing said process and said circuit means further for producing a second address segment which is derived from instructions in said process, said second address segment for addressing one of the registers in each of said communication register sets, bus circuitry connected to said communication registers, said communication index registers and said circuit means for conveying addresses and data associated with said communication registers, and means connected to said communication index registers, said circuit means and said bus circuitry for combining said first and second address segments to produce a composite address for one of said registers within said communication register sets, whereby one or more of said processors can communicate with a selected one of said communication register sets through said bus circuitry by use of said composite addresses for detecting a predetermined state for the semaphore register associated with said selected communication register set and said processors can obtain process state data from said selected communication register set for executing said process concurrently in more than one of said processors.
Claim 11
Dependent Claim
48 words
The multi-processor computer system as recited in Claim 7 including a second semaphore register associated with each of said communication register sets, said second semaphore registers for being set by one of said processors to prevent access to the corresponding communication register set by other of said processors.
Claim 12
Dependent Claim
26 words
The multi-processor computer system as recited in Claim 7 wherein said circuit means is an arithmetic logic unit which can generate addresses from said process instructions.
Claim 13
Dependent Claim
245 words
A multi-processor computer system for parallel execution of a process, comprising: a plurality of communication register sets, each set comprising a plurality of communication registers, at least one respective semaphore register associated with one register in each of said communication register sets, a respective process-independent communication index register associated with each of said processors, each of said communication index registers for storing a first address segment therein for addressing one of the communication register sets, respective circuit means associated with each of said processors for producing a second address segment which is derived from instructions in said process, said second address segment for addressing one of the registers in each of said communication register sets, bus circuitry connected to said communication registers, said communication index registers and said circuit means for conveying addresses and data associated with said communication registers, and means connected to said communication index registers, said circuit means and said bus circuitry for combining said first and second address segments to produce a composite address for one of said registers within said communication register sets, whereby more than one of said processors can communicate with a selected one of said communication register sets through said bus circuitry by use of said composite addresses for detecting a predetermined state for the semaphore register associated with said selected communication register set and obtaining process state data from said selected communication register set for executing said process concurrently in more than one of said processors.
Claim 14
Dependent Claim
245 words
A multi-processor computer system for parallel execution of a process, comprising: a plurality of communication register sets, each set comprising a plurality of communication registers, at least one respective semaphore register associated with one register in each of said communication register sets, a respective process-independent communication index register associated with each of said processors, each of said communication index registers for storing a first address segment therein for addressing one of the communication register sets, respective circuit means associated with each of said processors for producing a second address segment which is derived from instructions in said process, said second address segment for addressing one of the registers in each of said communication register sets, bus circuitry connected to said communication registers, said communication index registers and said circuit means for conveying addresses and data associated with said communication registers, and means connected to said communication index registers, said circuit means and said bus circuitry for combining said first and second address segments to produce a composite address for one of said registers within said communication register sets, whereby more than one of said processors can communicate with a selected one of said communication register sets through said bus circuitry by use of said composite addresses for detecting a predetermined state for the semaphore register associated with said selected communication register set and obtaining process state data from said selected communication register set for executing said process concurrently in more than one of said processors.
Claim 15
Dependent Claim
45 words
The multi-processor computer system recited in Claim 10 including a second semaphore register associated with each of said communication register sets, said second semaphore register set by one of said processors to prevent access to the corresponding communication register set by other of said processors.
Claim 16
Dependent Claim
25 words
The multi-processor computer system recited in Claim 10 wherein said circuit means is an arithmetic logic unit which can generate addresses from said process instructions.
References Cited (Backward Citations)
No citation records indexed.
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