EP0329418A2
Expired / Lapsed
EP
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Circuit synchronization system
Assignee: Graphics Properties Holdings Inc
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Filing: 1989-02-15
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Granted: —
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Expires: 2009-02-15
Abstract
Abstract A system for synchronizing the operation of a CPU and coprocessor operating from a common clock signal includes a first voltage controlled delay line (12) connected to receive the clock signal and delay it by a fixed time interval before supplying it to one of the CPU or coprocessor. A second voltage controlled delay line (22) is connected to receive the clock signal and delay it by an adjustable time interval before supplying it to the other of the CPU or coprocessor. The time interval of the second delay line is determined by the potential of a control signal generated from a phase locked loop circuit coupled to the output terminals of the CPU and coprocessor.
Inventors
- 👤 Mark G. Johnson
- 👤 Edwin L. Hudson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 23:46
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; G; G06; G06F; G06F7/00; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
129 words
A system for synchronizing a first and second circuit operating from a common clock signal and each producing output signals, the system comprising: first delay line means (12) connected to receive the common clock signal and delay it by a selected interval before supplying it to the first circuit; second delay line means (22) connected to receive the clock signal and delay it by an adjustable interval in response to a control signal before supplying it to the second circuit; and phase detection means (30) connected to both of the first and second circuits for detecting when each produces an output signal and in response supplying the control signal to the second delay line means, the control signal having a potential related to the difference between the output signals.
Claim 2
Independent Claim
129 words
A system for synchronizing a first and second circuit operating from a common clock signal and each producing output signals, the system comprising: first delay line means (12) connected to receive the common clock signal and delay it by a selected interval before supplying it to the first circuit; second delay line means (22) connected to receive the clock signal and delay it by an adjustable interval in response to a control signal before supplying it to the second circuit; and phase detection means (30) connected to both of the first and second circuits for detecting when each produces an output signal and in response supplying the control signal to the second delay line means, the control signal having a potential related to the difference between the output signals.
Claim 3
Dependent Claim
28 words
A system as claimed in claim 1 wherein the phase detection means (30) comprises means for detecting which of the output signals from the two circuits was earlier.
Claim 4
Dependent Claim
17 words
A system as claimed in claim 2 wherein the means for detecting comprises an edge-triggered flip-flop circuit.
Claim 5
Dependent Claim
40 words
A system as claimed in claim 1, 2 or 3 wherein the phase detection means comprises: filtering means (37) connected to receive the control signal and average it over time before supplying it to the second delay line means (22).
Claim 6
Dependent Claim
67 words
A system as claimed in claim 4 wherein the filtering means (37) comprises: a first current source switchably connected by a first switch between a storage capacitor and an upper potential source; a second current source switchably connected by a second switch between the storage capacitor and a lower potential source; and switching means responsive to the control signal for controlling the first and second current sources.
Claim 7
Dependent Claim
65 words
A system as claimed in claim 5 wherein the switching means comprises: a pulse generator for supplying pulses; a first gate connected to receive the pulses and the control signal and having a first output coupled to control the first switch; and a second gate connected to receive the pulses and a complementary control signal and having a second output coupled to the second switch.
Claim 8
Independent Claim
76 words
A system as claimed in any preceding claim wherein the first delay line comprises (12) comprises a first voltage-controlled delay line having a plurality of stages providing a range of time delays; wherein the second delay line means (22) comprises a second voltage-controlled delay line having a plurality of stages providing a range of time delays; and wherein the time delay of the first delay line is set to be midway in the range of delays.
Claim 9
Independent Claim
38 words
A system as claimed in any one of claims 1-6 wherein the second delay line means (22) comprises a voltage-controlled delay line for delaying the clock signal by a time related to the potential of the control signal.
Claim 10
Dependent Claim
70 words
A system as claimed in claim 8 wherein the second voltage-controlled delay line includes at least one stage comprising: an inverter having an input terminal connected to receive the clock signal and an output terminal; a resistor-capacitor network having a variable time constant, the network connected between the output terminal and a fixed potential; and control means connected to receive the control signal and in response vary the time constant.
Claim 11
Dependent Claim
53 words
A system as claimed in claim 9 wherein the network comprises: a capacitor having a first electrode connected to the fixed potential; and a transistor having a first electrode connected to the inverter, a second electrode to a second electrode of the capacitor, and a control electrode connected to receive the control signal.
Claim 12
Dependent Claim
19 words
A system as claimed in claim 9 or 10 wherein the voltage-controlled delay line comprises a plurality of stages.
Claim 13
Dependent Claim
17 words
A system as claimed in claim 11 wherein the delay line comprises an even number of stages.
References Cited (Backward Citations)
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