Digital signal processing apparatus

Claim 2

A digital signal processing apparatus comprising memory means which stores input information and reads out the stored information; a task controller which finds the quantity of valid information among information to be processed and produces address control signals for dividing the information to be processed into a plurality of divisions in a sense of adaptation so that a plurality of assigned quantities of valid information are even; and a plurality of digital signal processors which receive the address control signals from said task controller to adjust addresses of assigned areas to be processed, read information out of said memory means to implement coding processes, and output the results of processes.

Claim 3

A digital signal processing apparatus according to claim 1, wherein said memory means comprises a plurality of input memories provided in correspondence to said digital signal processors.

Claim 4

A digital signal processing apparatus comprising a multiprocessor module including a plurality of signal processors in connection, each of said signal processors including an instruction memory which stores a sub-program that describes a functional process of a signal processing operation that is a combination of the functional processes for data blocks formed of a plurality of data, said instruction memory being accessible for writing from outside and connected through an internal bus with a data memory which is used for the execution of said signal processing operation; a digital signal processor which executes any of said functional processes in units of data blocks in accordance with a sub-program stored in said instruction memory; block forming means which forms a signal processing block of one unit by appending, for each data block, control parameters including the type of functional process to be executed, a block address indicative of the position in time and spatial domains and the order in time and spatial domains of said data block and information indicative of post-process attributes of said data block; activation control means which analyzes said control parameters to activate each unit of said functional process indicated by said parameter; an interrupt controller which controls the timing of execution of said activation control means in response to an external interrupt; status indication means which indicates to the outside as to whether said functional process is in execution; a data input bus which reads out a unit of signal processing block from an external data memory by way of said internal bus for the execution of said functional process; at least one dual-port memory capable of reading and writing independently on both ports, with one port being connected to said internal bus and adapted to write a unit of signal process block resulting from said functional process, and with another port being opened to the outside; and an external bus controller including a bus contention control means which connects said internal bus to a common bus consisting of at least one data bus provided externally only when the common bus is not used by an external device and implementing data transfer for the unit of signal processing block or arbitrary quantity of data; and a transfer control means which performs data transfer asynchronously in units of signal processing block by linking adjoining ones of said signal processors in a serial and/or parallel arrangement by connecting the externally-opened port of said dual-port memory in one processor to said data input bus of another processor; an input frame buffer of dual-port memory which forms a digital signal into blocks and writes the signal on one port in units of frame or block on a realtime basis and implements data input by connecting another port to said input bus in the first-stage signal processor in said multiprocessor module; at least one common memory which is connected to said common bus and adapted to transact data in units of signal processing block or arbitrary number of data with all of said signal processors; a task table which memorizes said status indication means in said signal processors; an output controller which reads out the last-processed signal processing block written in said dual-port memory in the last-stage signal processor in said multiprocessor module, rearranges the block in accordance with said processing parameters so as to be in compliance with the position in time and spatial domains and the order in time and spatial domains, stores the rearrangement result temporarily in a buffer memory and outputs the buffer memory contents at a constant quantity per unit time; a data flow controller which scans the contents of said task table at a constant interval, determines the process assignments of said signal processors on the basis of feedback information such as the degree of occupancy of said buffer memory indicated by said output controller, and activates the interrupt controller of each said signal processor; and a writing means which newly generates said processing parameters for each signal processing block entered newly to said input frame buffer and writes the parameters in corresponding positions of input frame buffer.

Claim 5

A digital signal processing apparatus comprising a multiprocessor module including a plurality of signal processors in connection, each of said signal processors including an instruction memory which stores a sub-program that describes a functional process of a signal processing operation that is a combination of the functional processes for data blocks formed of a plurality of data, said instruction memory being accessible for writing from outside and connected through an internal bus with a data memory which is used for the execution of said signal processing operation; a digital signal processor which executes any of said functional processes in units of data blocks in accordance with a sub-program stored in said instruction memory; block forming means which forms a signal processing block of one unit by appending, for each data block, control parameters including the type of functional process to be executed, a block address indicative of the position in time and spatial domains and the order in time and spatial domains of said data block and information indicative of post-process attributes of said data block; activation control means which analyzes said control parameters to activate each unit of said functional process indicated by said parameter; an interrupt controller which controls the timing of execution of said activation control means in response to an external interrupt; status indication means which indicates to the outside as to whether said functional process is in execution; a data input bus which reads out a unit of signal processing block from an external data memory by way of said internal bus for the execution of said functional process; at least one dual-port memory capable of reading and writing independently on both ports, with one port being connected to said internal bus and adapted to write a unit of signal process block resulting from said functional process, and with another port being opened to the outside; and an external bus controller including a bus contention control means which connects said internal bus to a common bus consisting of at least one data bus provided externally only when the common bus is not used by an external device and implementing data transfer for the unit of signal processing block or arbitrary quantity of data; and a transfer control means which performs data transfer asynchronously in units of signal processing block by linking adjoining ones of said signal processors in a serial and/or parallel arrangement by connecting the externally-opened port of said dual-port memory in one processor to said data input bus of another processor; an input frame buffer of dual-port memory which forms a digital signal into blocks and writes the signal on one port in units of frame or block on a realtime basis and implements data input by connecting another port to said input bus in the first-stage signal processor in said multiprocessor module; at least one common memory which is connected to said common bus and adapted to transact data in units of signal processing block or arbitrary number of data with all of said signal processors; a task table which memorizes said status indication means in said signal processors; an output controller which reads out the last-processed signal processing block written in said dual-port memory in the last-stage signal processor in said multiprocessor module, rearranges the block in accordance with said processing parameters so as to be in compliance with the position in time and spatial domains and the order in time and spatial domains, stores the rearrangement result temporarily in a buffer memory and outputs the buffer memory contents at a constant quantity per unit time; a data flow controller which scans the contents of said task table at a constant interval, determines the process assignments of said signal processors on the basis of feedback information such as the degree of occupancy of said buffer memory indicated by said output controller, and activates the interrupt controller of each said signal processor; and a writing means which newly generates said processing parameters for each signal processing block entered newly to said input frame buffer and writes the parameters in corresponding positions of input frame buffer.

Claim 6

A digital signal processing apparatus according to claim 3, wherein said data flow controller comprises judgment means which judges the processing status of each processor by scanning said task table at a constant interval; and first control means which determines on the basis of the result provided by said judgment means as to whether each signal processing module can process a next signal processing block, and, if possible, issues an interrupt signal to said interrupt controller to initiate processing or, if impossible, directs a signal processing module, which can have a process, to transfer said signal processing block.

Claim 7

A digital signal processing apparatus according to claim 4, wherein said judgment means performs scanning, in case of parallel processing in a constant period, in a time length which is the input period of said signal processing block multiplied by the number of parallel processings, or, in case of serial processing, in a time length which is the input period divided by an integer greater than or equal to one, and implements matching with real time by being in synchronism with input data frames.

Claim 8

A digital signal processing apparatus according to claim 3, 4 or 5, wherein said data flow controller includes second control means, in which a piece of image data is divided into small rectangular blocks to form said data blocks, the size of data block is made equal to a maximum or minimum size dealt with by said functional processes and positions of small blocks in said piece of image data are used as spatial position information of said process parameters, and, in case of inter-frame coding for a moving image, a frame memory for storing a coded previous frame image is said common memory and a signal processing block processed by a signal processor unit is written in the position of the common memory by way of said common bus thereby to form feedback data, and a new image frame is processed by making reference to said feedback data from another signal processing block by way of the common bus; and third control means which, if feedback data of the previous frame has not yet written in the position in the common memory, dictates an execution wait for the process.

Claim 9

A digital signal processing apparatus according to claim 6, wherein a plurality of digital signal processors are connected in parallel through a local common bus, a local signal processor is formed of a local data flow controller which performs only process activation control for said digital signal processors, a local common memory which can be accessed commonly by said digital signal processors, and a plurality of digital signal processors, a plurality of local signal processors being connected to complete said signal processors in a hierarchical structure.

Claim 10

A digital signal processing apparatus according to claim 7, wherein said multiprocessor module is one in number.

Claim 11

A digital signal processing apparatus according to claim 7, wherein said multiprocessor module is more than one in number.

Claim 12

A digital signal processing apparatus comprising a first through third address generators which generate independently addresses for read data; a fourth address generator which generates write address information indicative of a write data destination and address; a first through third data memory, from which data are read out in accordance with addresses of said first through third address generators and to which data are written in accordance with address information of said fourth address generator; an operator which performs an arithmetic/logic operation for a pair of data selected by a first selector group under control of microprogram from among a first data pair consisting of data of said first data memory and data of said second data memory and a second data pair consisting of data of said third data memory and output data of a multiplier; a second selector group which selects one of said first data pair, and a third data pair consisting of data of said third data memory and output data of said operator under control of said microprogram so that a selected data pair is subjected to a multiplication operation by said multiplier; an output selector which selects one of the output of said operator and the output of said multiplier and transfers the selected output data over said first data through third data memories or a data bus to/an external circuit; and an accumulator which provides an output for the addition operation by an adder for cumulation of output value, holds cumulatively the result of addition by said adder, and transfers the output as write data to said first through third data memories or an external circuit.

Claim 13

A digital signal processing apparatus comprising a first through third address generators which generate independently addresses for read data; a fourth address generator which generates write address information indicative of a write data destination and address; a first through third data memory, from which data are read out in accordance with addresses of said first through third address generators and to which data are written in accordance with address information of said fourth address generator; an operator which performs an arithmetic/logic operation for a pair of data selected by a first selector group under control of microprogram from among a first data pair consisting of data of said first data memory and data of said second data memory and a second data pair consisting of data of said third data memory and output data of a multiplier; a second selector group which selects one of said first data pair, and a third data pair consisting of data of said third data memory and output data of said operator under control of said microprogram so that a selected data pair is subjected to a multiplication operation by said multiplier; an output selector which selects one of the output of said operator and the output of said multiplier and transfers the selected output data over said first data through third data memories or a data bus to/an external circuit; and an accumulator which provides an output for the addition operation by an adder for cumulation of output value, holds cumulatively the result of addition by said adder, and transfers the output as write data to said first through third data memories or an external circuit.

Claim 14

A digital signal processing apparatus according to claim 10, wherein said first through third address generators have an auto-increment mode for addressing.

Claim 15

A motion compensative operation method wherein a current input frame of digital image data consisting of a plurality of frames entered successively is divided into a plurality of blocks, and, in detecting a block which provides a minimal distortion resulting from computation of resemblance between patterns based on the cumulation of differential absolute values or differential square values of pixels in block between a block of the current input frame and blocks of M in number (M is a positive integer) of the previous frame, a maximum of K (K is an integer greater than or equal to one and smaller than or equal to the number of a total number of pixels in one block) pixels are used for the pattern resemblance computation, intermediate checks are conducted n times (n is an integer greater than or equal to one) during the resemblance computation at time points when the number of reference pixels is smaller than K, a block is determined to be outside the range of comparison for finding a minimal distortion block if a cumulative value at each time point is greater than a threshold value preset for each intermediate check time point, and a block having a minimal distortion is detected by computation from among blocks whose cumulative values are below the threshold values at all time points of intermediate checks.

Claim 16

A motion compensative operation method wherein a current input frame of digital image data consisting of a plurality of frames entered successively is divided into a plurality of blocks, and, in detecting a block which provides a minimal distortion resulting from computation of resemblance between patterns based on the cumulation of differential absolute values or differential square values of pixels in block between a block of the current input frame and blocks of M in number (M is a positive integer) of the previous frame, a maximum of K (K is an integer greater than or equal to one and smaller than or equal to the number of a total number of pixels in one block) pixels are used for the pattern resemblance computation, intermediate checks are conducted n times (n is an integer greater than or equal to one) during the resemblance computation at time points when the number of reference pixels is smaller than K, a block is determined to be outside the range of comparison for finding a minimal distortion block if a cumulative value at each time point is greater than a threshold value preset for each intermediate check time point, and a block having a minimal distortion is detected by computation from among blocks whose cumulative values are below the threshold values at all time points of intermediate checks.