EP0328331A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor device and method of manufacturing the same
Assignee: Toshiba Corp
•
Filing: 1989-02-06
•
Granted: —
•
Expires: 2009-02-06
Abstract
Abstract A semiconductor device includes a semiconductor substrate, a pair of low breakdown voltage elements formed in the substrate so as to be adjacent to each other, and a high breakdown voltage element formed to be adjacent to one of the low breakdown voltage elements. The pair of low breakdown voltage elements are isolated from each other by a pn junction and the one of the low breakdown voltage elements and the high breakdown voltage element are isolated from each other by a dielectric material. The semiconductor substrate is a composite substrate formed by directly bonding a first substrate serving as an element region to a second substrate serving as a supporting member through an insulating film.
Inventors
- 👤 Akio C/O Patent Division Nakagawa
- 👤 Kazuyoshi C/O Patent Division Furukawa
- 👤 Tsuneo C/O Patent Division Ogura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 01:24
CPC Classifications
H; H10; H10D; H10D12/00; H10D12/411; H10D12/421; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D86/00; H10D86/201; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/031; H10W10/041; H10W10/061; H10W10/10; H10W10/181; H10W10/30; H10W10/40; H10P90/1914; Y; Y10; Y10S; Y10S148/00; Y10S148/012
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
85 words
A semiconductor device comprising a semiconductor substrate, a pair of low breakdown voltage elements formed on said substrate so as to be adjacent to each other, and a high breakdown voltage element formed to be adjacent to one of said low breakdown voltage elements, wherein said pair of low breakdown voltage elements are isolated from each other by a pn junction and the one of said low breakdown voltage elements and said high breakdown voltage element are isolated from each other by a dielectric material.
Claim 2
Dependent Claim
85 words
A semiconductor device comprising a semiconductor substrate, a pair of low breakdown voltage elements formed on said substrate so as to be adjacent to each other, and a high breakdown voltage element formed to be adjacent to one of said low breakdown voltage elements, wherein said pair of low breakdown voltage elements are isolated from each other by a pn junction and the one of said low breakdown voltage elements and said high breakdown voltage element are isolated from each other by a dielectric material.
Claim 3
Dependent Claim
44 words
A device according to claim 1, characterized in that said semiconductor substrate is a composite substrate formed by directly bonding a first substrate serving as an element region to a second substrate serving as a supporting member with a first insulating film interposed therebetween.
Claim 4
Dependent Claim
44 words
A device according to claim 2, characterized in that said first substrate of said composite substrate is divided into a first and second island regions which are isolated from each other by a second insulating film formed on an inner surface of a groove.
Claim 5
Dependent Claim
24 words
A device according to claim 3, characterized in that said second insulating film has a thickness larger than that of said first insulating film.
Claim 6
Dependent Claim
48 words
A device according to claim 3, characterized in that said high breakdown voltage element is formed in said first island region, said low breakdown voltage elements are formed in said second island region, and said low breakdown voltage elements are isolated from each other by a pn junction.
Claim 7
Dependent Claim
90 words
A device according to claim 5, characterized in that said second island region is of a first conductivity type, a first well of the first conductivity type and a second well of a second conductivity type are formed in said second island region, a lateral or vertical type bipolar transistor is formed in said first well, and a lateral or vertical type bipolar transistor having a conductivity type structure different from that of said lateral or vertical type bipolar transistor in said first well is formed in said second well.
Claim 8
Dependent Claim
18 words
A device according to claim 5, characterized in that said first and second wells have tapered side walls.
Claim 9
Dependent Claim
75 words
A device according to claim 5, characterized in that said second island region is of the first conductivity type, first well of the first conductivity type and a second well of the second conductivity type are formed in said second island region, a first MOS transistor is formed in said first well, and a second MOS transistor of a channel conductivity different from that of said first MOS transistor is formed in said second well.
Claim 10
Dependent Claim
60 words
A device according to claim 5, characterized in that said second island region is of the first conductivity type, a well of the second conductivity type is formed in said second island region, and a first bipolar transistor and a second bipolar transistor which is isolated from said first bipolar transistor by a pn junction are formed in said well.
Claim 11
Dependent Claim
45 words
A device according to claim 5, characterized in that no insulating film is present on a bonding interface between said first island region and said second substrate, and a vertical type device as a high breakdown voltage element is formed in said first island region.
Claim 12
Dependent Claim
42 words
A device according to claim 10, characterized in that said vertical type device is the one selected from the group consisting of a MOS transistor, MOS thyristor, insulated gate bipolar transistor, bipolar transistor, thyristor, gate turn-off thyristor, and MOS gate turn-off thyristor.
Claim 13
Dependent Claim
26 words
A device according to claim 5, characterized in that a space is formed in a bonding interface between said first island region and said second substrate.
Claim 14
Independent Claim
205 words
A method of manufacturing a semiconductor substrate comprising the steps of mirror-polishing one surface of each of a first semiconductor substrate of a first conductivity type and a second semiconductor substrate, forming a first impurity region of the first conductivity type in the mirror-polished surface of said first semiconductor substrate, forming a first insulating film on at least one of a surface of said first impurity region and the mirror-polished surface of said second semiconductor substrate, forming a composite substrate by directly bonding the mirror-polished surface of said first semiconductor substrate to the mirror-polished surface of said second substrate, controlling a thickness of said first semiconductor substrate, forming a groove by selectively etching a portion of said first semiconductor substrate of said composite substrate, forming second impurity regions by diffusing an impurity of the first conductivity type in side walls of a plurality of semiconductor layers which are isolated from each other by said groove, forming a second insulating film in surfaces of said second impurity regions, forming a high breakdown voltage element in one of said semiconductor layers, and forming a plurality of low breakdown voltage elements which are isolated from each other by a pn junction in the other of said semiconductor layers.
Claim 15
Independent Claim
205 words
A method of manufacturing a semiconductor substrate comprising the steps of mirror-polishing one surface of each of a first semiconductor substrate of a first conductivity type and a second semiconductor substrate, forming a first impurity region of the first conductivity type in the mirror-polished surface of said first semiconductor substrate, forming a first insulating film on at least one of a surface of said first impurity region and the mirror-polished surface of said second semiconductor substrate, forming a composite substrate by directly bonding the mirror-polished surface of said first semiconductor substrate to the mirror-polished surface of said second substrate, controlling a thickness of said first semiconductor substrate, forming a groove by selectively etching a portion of said first semiconductor substrate of said composite substrate, forming second impurity regions by diffusing an impurity of the first conductivity type in side walls of a plurality of semiconductor layers which are isolated from each other by said groove, forming a second insulating film in surfaces of said second impurity regions, forming a high breakdown voltage element in one of said semiconductor layers, and forming a plurality of low breakdown voltage elements which are isolated from each other by a pn junction in the other of said semiconductor layers.
Claim 16
Dependent Claim
23 words
A method according to claim 13, characterized in that said first insulating film is formed on the surface of said first impurity region.
Claim 17
Dependent Claim
15 words
A method according to claim 13, characterized in that said etching is an anisotropic etching.
Claim 18
Dependent Claim
24 words
A method according to claim 13, characterized in that said second insulating film has a thickness larger than that of said first insulating film.
Claim 19
Independent Claim
213 words
A method of manufacturing a semiconductor substrate comprising the steps of mirror-polishing one surface of each of a first semiconductor substrate of a first conductivity type and a second semiconductor substrate, forming a first impurity region of the first conductivity type in the mirror-polished surface of said first semiconductor substrate, forming a first insulating film on at least one of a surface of said first impurity region and the mirror-polished surface of said second semiconductor substrate, forming a composite substrate by directly bonding the mirror-polished surface of said first semiconductor substrate to the mirror-polished surface of said second substrate, controlling a thickness of said first semiconductor substrate, forming a groove by selectively etching a portion of said first semiconductor substrate of said composite substrate, forming second impurity regions by diffusing an impurity of the first conductivity type in side walls of a plurality of semiconductor layers which are isolated from each other by said groove, forming a second insulating film in surfaces of said second impurity regions, forming a high breakdown voltage element in one of said semiconductor layers, forming a plurality of wells which are isolated from each other by a pn junction in the other of said semiconductor layers, and forming a low breakdown voltage element in each of said wells.
Claim 20
Independent Claim
213 words
A method of manufacturing a semiconductor substrate comprising the steps of mirror-polishing one surface of each of a first semiconductor substrate of a first conductivity type and a second semiconductor substrate, forming a first impurity region of the first conductivity type in the mirror-polished surface of said first semiconductor substrate, forming a first insulating film on at least one of a surface of said first impurity region and the mirror-polished surface of said second semiconductor substrate, forming a composite substrate by directly bonding the mirror-polished surface of said first semiconductor substrate to the mirror-polished surface of said second substrate, controlling a thickness of said first semiconductor substrate, forming a groove by selectively etching a portion of said first semiconductor substrate of said composite substrate, forming second impurity regions by diffusing an impurity of the first conductivity type in side walls of a plurality of semiconductor layers which are isolated from each other by said groove, forming a second insulating film in surfaces of said second impurity regions, forming a high breakdown voltage element in one of said semiconductor layers, forming a plurality of wells which are isolated from each other by a pn junction in the other of said semiconductor layers, and forming a low breakdown voltage element in each of said wells.
Claim 21
Dependent Claim
34 words
A method according to claim 17, characterized in that said plurality of wells are formed by forming a plurality of grooves in prospective well regions by selective etching and burying semiconductors in said grooves.
Claim 22
Dependent Claim
24 words
A method according to claim 17, characterized in that said plurality of wells are formed by selectively diffusing an impurity in prospective well regions.
Claim 23
Dependent Claim
29 words
A method according to claim 17, characterized in that a plurality of low breakdown voltage elements isolated from each other by a pn junction are formed in said well.
Claim 24
Dependent Claim
23 words
A method according to claim 17, characterized in that said first insulating film is formed on the surface of said first impurity region.
Claim 25
Dependent Claim
24 words
A method according to claim 17, characterized in that said second insulating film has a thickness larger than that of said first insulating film.
Claim 26
Independent Claim
259 words
A method of manufacturing a semiconductor substrate comprising the steps of mirror-polishing one surface of each of a first semiconductor substrate of a first conductivity type and a second semiconductor substrate, forming a first impurity region of the first conductivity type in the mirror-polished surface of said first semiconductor substrate, forming a first insulating film on at least one of a surface of said first impurity region and the mirror-polished surface of said second semiconductor substrate, forming a composite substrate by directly bonding the mirror polished surface of said first semiconductor substrate to the mirror-polished surface of said second substrate, controlling a thickness of said first semiconductor substrate, forming a first groove which reaches said first insulating film and a plurality of second grooves which do not reach said first impurity region by selectively etching a portion of said first semiconductor substrate of said composite substrate, said second substrate being divided into a first semiconductor region and a second semiconductor region having said second groove, which are isolated from each other by said first groove, forming second impurity regions by diffusing an impurity in side walls of said first and second grooves, forming a second insulating film in a surface of said second impurity region in said first groove, burying a solid material layer in said first groove and a semiconductor material layer in said second grooves, forming a high breakdown voltage element in said first semiconductor region, and forming low breakdown voltage elements which are isolated from each other by a pn junction in said semiconductor material layers.
Claim 27
Independent Claim
259 words
A method of manufacturing a semiconductor substrate comprising the steps of mirror-polishing one surface of each of a first semiconductor substrate of a first conductivity type and a second semiconductor substrate, forming a first impurity region of the first conductivity type in the mirror-polished surface of said first semiconductor substrate, forming a first insulating film on at least one of a surface of said first impurity region and the mirror-polished surface of said second semiconductor substrate, forming a composite substrate by directly bonding the mirror polished surface of said first semiconductor substrate to the mirror-polished surface of said second substrate, controlling a thickness of said first semiconductor substrate, forming a first groove which reaches said first insulating film and a plurality of second grooves which do not reach said first impurity region by selectively etching a portion of said first semiconductor substrate of said composite substrate, said second substrate being divided into a first semiconductor region and a second semiconductor region having said second groove, which are isolated from each other by said first groove, forming second impurity regions by diffusing an impurity in side walls of said first and second grooves, forming a second insulating film in a surface of said second impurity region in said first groove, burying a solid material layer in said first groove and a semiconductor material layer in said second grooves, forming a high breakdown voltage element in said first semiconductor region, and forming low breakdown voltage elements which are isolated from each other by a pn junction in said semiconductor material layers.
Claim 28
Dependent Claim
27 words
A method according to claim 23, characterized in that said solid material layer and said semiconductor material layer are simultaneously buried in said first and second grooves.
Claim 29
Dependent Claim
23 words
A method according to claim 24, characterized in that said solid material is polycrystalline silicon and said semiconductor material is silicon formed epitaxially.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.