EP0327839A2 — Information handling system

Claim 1

Independent Claim 435 words

Virtual address translation control means for a logical storage operand address in a data processing system having at least one central processor (CP) with a predetermined number of general purpose registers (GPRs), some instructions of the CP specifying a general purpose register (GPR) address as a base general purpose register (GPR) address or as a non-base general purpose register (GPR) address, the base general purpose register (GPR) address locating a general purpose register GPR) having contents that take part in a calculation of an instruction's logical storage operand address from an instruction's operand address components including at least a base general purpose register (GPR) and optionally including either one or both of a non-base general purpose register (GPR) and a displacement field, the effective logical storage operand address being generated by means of the addition of the content of the base GPR and the content of any non-base GPR and any displacement field, characterized by means in the central processor (CP) for detecting a base general purpose register (GPR) address in an instruction, including instruction operation code decoding means for signalling whether a general purpose register (GPR) designation in an instruction is a base general purpose register (GPR) address or a non-base general purpose register (GPR) address, by means for selecting an access register (AR) with the base general purpose register (GPR) address pro vided by the detecting means, and the selecting means not selecting an AR with a non-base general purpose register (GPR) address provided by the detecting means, by a plurality of access registers (AR's), each access register (AR) being loadable with an address space identifying access list entry token (ALET) for locating an access list entry and an address space number second table entry, by address space number second table entry (ASTE) means for containing a segment table designation (STD) for dynamic address translation (DAT) and for holding and comparing an address space number second table entry (ASTE) sequence number (ASTESN) value in said access list, whereby if said comparison is true said segment table designation (STD) is released for use in accessing a predetermined authorized address space, by virtual address translation means receiving the effective logical storage operand address and an segment table designation (STD) from the address space number (ASN) second table entry (ASTE) means to locate a translation table and using the translation table to translate the effective logical storage operand address to a real address in a main storage of the data processing system, and whereby plural acessess registers (ARs) containing different acess list entry tokens (ALETs) enable the data processing system to concurrently access plural address spaces.

Claim 2

Dependent Claim 435 words

Virtual address translation control means for a logical storage operand address in a data processing system having at least one central processor (CP) with a predetermined number of general purpose registers (GPRs), some instructions of the CP specifying a general purpose register (GPR) address as a base general purpose register (GPR) address or as a non-base general purpose register (GPR) address, the base general purpose register (GPR) address locating a general purpose register GPR) having contents that take part in a calculation of an instruction's logical storage operand address from an instruction's operand address components including at least a base general purpose register (GPR) and optionally including either one or both of a non-base general purpose register (GPR) and a displacement field, the effective logical storage operand address being generated by means of the addition of the content of the base GPR and the content of any non-base GPR and any displacement field, characterized by means in the central processor (CP) for detecting a base general purpose register (GPR) address in an instruction, including instruction operation code decoding means for signalling whether a general purpose register (GPR) designation in an instruction is a base general purpose register (GPR) address or a non-base general purpose register (GPR) address, by means for selecting an access register (AR) with the base general purpose register (GPR) address pro vided by the detecting means, and the selecting means not selecting an AR with a non-base general purpose register (GPR) address provided by the detecting means, by a plurality of access registers (AR's), each access register (AR) being loadable with an address space identifying access list entry token (ALET) for locating an access list entry and an address space number second table entry, by address space number second table entry (ASTE) means for containing a segment table designation (STD) for dynamic address translation (DAT) and for holding and comparing an address space number second table entry (ASTE) sequence number (ASTESN) value in said access list, whereby if said comparison is true said segment table designation (STD) is released for use in accessing a predetermined authorized address space, by virtual address translation means receiving the effective logical storage operand address and an segment table designation (STD) from the address space number (ASN) second table entry (ASTE) means to locate a translation table and using the translation table to translate the effective logical storage operand address to a real address in a main storage of the data processing system, and whereby plural acessess registers (ARs) containing different acess list entry tokens (ALETs) enable the data processing system to concurrently access plural address spaces.

Claim 3

Dependent Claim 107 words

Virtual address translation control means of claim 1 characterized by an access register translation lookaside buffer (ALB) connected to receive access list entry tokens (ALETs) from said access register (AR) registers and the results of access register translation (ART) from said ASN second table entry (ASTE) and for storing said results, means for creating a TAG identifier for each access list entry sequence number (ALET) and for each access register translation (ART) result so that when a particular access list entry token (ALET) is used again the correct access register translation (ART) result will be supplied so that access register translation (ART) does not have to occur.

Claim 4

Dependent Claim 121 words

Virtual address translation control means of claim 1 characterized by program status word (PSW) means in said central processor (CP) for controlling the function of said central processor (CP) in response to a current program status word (PSW) in said means, means responsive to said program status word (PSW) means to begin and end access register mode of operation in response to the contents of a preselected portion of said program status word (PSW), said access registers(ARs) retaining their contents if access register (AR) mode is ended to preserve their contents until access register (AR) mode is resumed so that another machine function may occur in non-access-register (AR) mode and allow access register (AR) mode to resume in the preserved status.

Claim 5

Dependent Claim 93 words

Virtual address translation control means of claim 1 for each access register (AR) and characterized by dispatchable unit access list (DUAL) to be identified with the work unit being handled, a primary space access list (PSAL) to be identified with the program performing the service, and means for determining from said access list entry token (ALET) whether the dispatchable unit access list (DUAL) or the primary space access list (PSAL) is to be used and for selecting the access list entry (ALE) from the proper access list (AL) for access register translation (ART).

Claim 6

Dependent Claim 188 words

Virtual address translation control means characterized by a plurality of general purpose register (GPR) means for containing a first component of a virtual address, a plurality of access register means each associated with a particular one of said general register means, each of said access register (AR) means having the capability of holding an access list entry token (ALET), an access list means containing access list entries each identified by an access list entry token (ALET), means for obtaining an access list entry (ALE) corresponding to an access list entry token (ALET) in an access register (AR) means at the time the associated general purpose register (GPR) means is activated in an addressing operation, address space number second table means for containing address space number second table entries (ASTE), means for identifying an access second table entry (ASTE) from said access list entry (ALE) and for obtaining said access second table entry (ASTE), wherein said access second table entry (ASTE) contains a second component for virtual address translation, and virtual address translation means for using said first and second components for virtual address translation to obtain real addresses.

Claim 7

Dependent Claim 188 words

Virtual address translation control means characterized by a plurality of general purpose register (GPR) means for containing a first component of a virtual address, a plurality of access register means each associated with a particular one of said general register means, each of said access register (AR) means having the capability of holding an access list entry token (ALET), an access list means containing access list entries each identified by an access list entry token (ALET), means for obtaining an access list entry (ALE) corresponding to an access list entry token (ALET) in an access register (AR) means at the time the associated general purpose register (GPR) means is activated in an addressing operation, address space number second table means for containing address space number second table entries (ASTE), means for identifying an access second table entry (ASTE) from said access list entry (ALE) and for obtaining said access second table entry (ASTE), wherein said access second table entry (ASTE) contains a second component for virtual address translation, and virtual address translation means for using said first and second components for virtual address translation to obtain real addresses.

Claim 8

Dependent Claim 99 words

Virtual address translation control means of claim 5 and for each address register (AR) characterized by a dispatchable unit access list (DUAL) to be associated with the work unit being handled, a primary space access list (PSAL) to be associated with the primary address space of the program performing the service, and means for determining from said access list entry token (ALET) whether the dispatchable unit access list (DUAL) or the primary space access list (PSAL) is to be used and for selecting said access list entry (ALE) from the proper access list (AL) for access register translation (ART).

Claim 9

Dependent Claim 75 words

Virtual address translation control means of claim 5 characterized by means for determining if an access list entry token (ALET) is a predetermined value, control register means for containing a preselected second component value for virtual address translation, and means for providing from said control register means said preselected second component value to said virtual address translation means if said means for determining finds that said access list entry token (ALET) is said predetermined value.

Claim 10

Dependent Claim 93 words

Virtual address translation control means of claim 7 characterized by a dispatchable unit access list (DUAL) to be associated with the work unit being handled, a primary space access list (PSAL) to be associated with the primary address space of the program performing the service, and means for determining from said access list entry token (ALET) whether the dispatchable unit access list (DUAL) or the primary space access list (PSAL) is to be used and for selecting said access list entry (ALE) from the proper access list (AL) for access register translation (ART).

Claim 11

Dependent Claim 106 words

Virtual address translation control means of claim 8 characterized by an access register translation lookaside buffer (ALB) connected to receive access list entry tokens (ALETs) from said access registers (AR) and the results of access register translation (ART) from said access ASN second table entry (ASTE) and for storing said results, means for creating a TAG identifier for each access list entry token (ALET) and for each access register translation (ART) result so that when a particular access list entry token (ALET) is used again the correct access register translation (ART) result will be supplied so that access register translation (ART) does not have to occur.

Claim 12

Dependent Claim 133 words

Method of access register translation for the virtual address translation control means according to claim 1 characterized by steps of: a. determining from an address portion of the contents of the access register (AR) an access list entry in an access list specified by the contents of the access register (AR) by means of a predetermined arithmetic process; b. determining from the contents of the access list entry identified in step a., an address space second table entry (ASTE) in said memory means; c. determining from the address space second table entry (ASTE) identified in step b., a segment table designation, and d. determining from the contents of the general purpose register (GPR) means and the segment table designation (STD) identified in step c., a real address using said virtual address translating means.

Claim 13

Dependent Claim 62 words

Method of claim 10 characterized by a.(1) verifying the access list entry determined in step a., by comparing an identity portion of said access register (AR) contents with a corresponding identity portion of said access list entry, and a.(2) creating an exception condition if the comparison does not agree or proceeding with additional steps in the translation process if the comparison agrees.

Claim 14

Dependent Claim 68 words

Method of claim 10 characterized by b.(1) verifying the authority to use the ASN second table entry (ASTE) identified in step b. by comparing an identity portion of the ASN second table entry (ASTE) with an identity portion of the access list entry, and b.(2) creating an exception condition if the comparison does not agree or proceeding with additional steps in the translation process if the comparison agrees.

Claim 15

Dependent Claim 89 words

Method of claim 10 characterized by determining from the contents of said access register (AR) an access list identifier means to determine if the access list identified in the access register (AR) is the dispatchable unit access list or the primary space access list, and determining from a first preselected control register the location of the dispatchable unit access list or from a second preselected control register the location of the primary space access list as identified from the contents of the access register (AR) in the preceding step.

Claim 16

Dependent Claim 62 words

Method of claim 13 characterized by a.(1) verifying the access list entry determined in step a., by comparing an identity portion of said access register (AR) contents with a corresponding identity portion of said access list entry, and a.(2) creating an exception condition if the comparison does not agree or proceeding with additional steps in the translation process if the comparison agrees.

Claim 17

Dependent Claim 68 words

Method of claim 14 characterized by b.(1) verifying the authority to use the ASN second table entry (ASTE) identified in step b. by comparing an identity portion of the ASN second table entry (ASTE) with an identity portion of the access list entry, and b.(2) creating an exception condition if the comparison does not agree or proceeding with additional steps in the translation process if the comparison agrees.

Claim 18

Dependent Claim 62 words

Method of claim 15 characterized by a.(1) verifying the access list entry determined in step a., by comparing an identity portion of said access register (AR) contents with a corresponding identity portion of said access list entry, and a.(2) creating an exception condition if the comparison does not agree or proceeding with additional steps in the translation process if the comparison agrees.

Claim 19

Dependent Claim 169 words

Method of claim 10 characterized by e. providing to said access register translation lookaside buffer (ALB) each time an access list entry token (ALET) is issued from an access register (AR) a copy of the access list entry token (ALET); f. providing an segment table designation (STD) for virtual addresstranslation from said access register translation lookaside buffer (ALB) if said access list entry token (ALET) is in said access register translation lookaside buffer (ALB) and if the resulting segment table designation (STD) from a previous access register translation (ART) is in said access register translation lookaside buffer (ALB); g. storing said acess list entry token (ALET) in said access register translation lookaside buffer (ALB) if said access list entry token (ALET) is not already stored in said access register translation lookaside buffer (ALB) and also storing the results of the access register translation (ART) operation on said access list entry token (ALET) so that said results can be provided when said access list entry token (ALET) is again issued.

Claim 20

Dependent Claim 73 words

Method of claim 10 characterized by a.(3) determining from a private identifier portion of said access list entry (ALE) determined in step a., if the access list entry (ALE) may be used by any user or if the authority mechanism must be used, and a.(4) proceeding with further steps if the access list entry (ALE) may be used by any user or using the authority mechanism if the private identifier mechanism so requires.

Claim 21

Dependent Claim 56 words

Method of claims 10 or 18characterized by a.(5) determining if the contents of said address register (AR) matches one or more predetermined values, and b.(6) selecting a specified one of said control registers containing an segment table designation (STD) for use in virtual address translation corresponding to the particular predetermined value in said address register (AR).

Claim 22

Dependent Claim 104 words

Method of claim 19 characterized in that if the access register (AR) does not contain one or more predetermined values, then; determining from the contents of said access register (AR) an access list identifier means to determine if the access list identified in the access register (AR) is the dispatchable unit access list or the primary space access list, and determining from a first preselected control register the location of the dispatchable unit access list or from a second preselected control register the location of the primary space access list as identified from the contents of the access register (AR) in the preceding step.

Claim 23

Dependent Claim 316 words

Virtual address translation control means as set forth in claims 1 to 20, characterized by an access register translation (ART) mechanism with a plurality of general purpose register (GPR) means for containing a first component of a virtual address, a plurality of access register (AR) means each associated with a particular one of said general register means, each of said access register (AR) means having the capability of holding an access list entry token (ALET), an access list (AL) means containing access list entries (ALE) each identified by an access list entry token (ALET), means for obtaining an access list entry (ALE) corresponding to an access list entry token (ALET) in an access register (AR) means at the time the associated general purpose register for containing operands and addresses (GPR) means is activated in an addressing operation, memory means for containing address space second table entries (ASTE), means for identifying an ASN second table entry (ASTE) entry from said access list entry (ALE) and for obtaining said ASN second table entry (ASTE) from said memory means, wherein said ASN second table entry (ASTE) contains a second component for virtual address translation, access register translation (ART) lookaside buffer (ALB) means connected to receive access list entry tokens (ALETs) from said access register (AR) means, access list entrys (ALEs) from said access list (AL) means and ASN second table entrys (ASTEs) from said memory means and for storing said access list entry tokens (ALET)s, access list entrys (ALEs) and ASN second table entrys (ASTEs) to provide said second component for virtual address translation in response to an input from an access register (AR) so that said access list (AL) and said memory means will not be accessed if corresponding entries are present in said ART lookaside buffer (ALB), and virtual address translation means for using said first and second components for virtual address translation to obtain real addresses.

Claim 24

Dependent Claim 105 words

Virtual address translation control means as set forth in claims 1 to 20, characterized by ALB-ALD/ALE table means for providing an ASN second table entry (ASTE) address in response to an input from an access register (AR), if said ALB-ALD/ALE table means contains an entry corresponding to said access register (AR) input and ALB-ASTE table means for providing said second component for virtual address translation in response to an ASN second table entry (ASTE) address input from said ALB-ALD/ALE table means, wherein said ALB-ALD/ALE table means contains one or more entries having ASN second table entry (ASTE) addresses which locate an ALB-ASTE table means entry.

Claim 25

Dependent Claim 66 words

Virtual address translation control means of claim 22 wherein said ART lookaside buffer (ALB) is further comprised of: ALB-ATE table means for checking authority to use an ALB-ASTE table means entry wherein said ALB-ATE uses an ATO obtained from said ALB-ASTE table entry and an extended authorization index (EAX) obtained from a control register as index terms to locate and provide an authority indicating output (S-bit).

Claim 26

Dependent Claim 104 words

Virtual address translation control means of claim 22 characterized by a dispatchable unit access list (DUAL) to be identified with the work unit being handled, a primary space access list (PSAL) to be identified with the program performing the service, and means for determining from said access list entry token (ALET) whether the dispatchable unit access list (DUAL) or the primary space access list (PSAL) is to be used and for providing said access list entry token (ALET) to the proper access list (AL) for access register translation (ART) or to the ART lookaside buffer (ALB) to provide the required second component if present.

Claim 27

Dependent Claim 75 words

Virtual address translation control means of claim 22 characterized by means for determining if an access list entry token (ALET) is a predetermined value, control register means for containing a preselected second component value for virtual address translation, and means for providing from said control register means said preselected second component value to said virtual address translation means if said means for determining finds that said access list entry token (ALET) is said predetermined value.

Claim 28

Dependent Claim 209 words

Method of access register translation (ART) for the virtual address translation control means according to claim 10 characterized by a. determining from an address portion of the contents of the access register (AR) an access list entry in an access list specified by the contents of the access register (AR) by means of a predetermined arithmetic process; b. determining from the contents of the access list entry identified in step a., an address space number second table entry (ASTE) in said means for assigning and storing ASN second table entry (ASTE) entries; c. determining from the ASN second table entry (ASTE) identified in step b., a segment table designation; d. storing in said ART lookaside buffer (ALB) a representation of the contents of said access register (AR) means, said access list entry and said ASN second table entry (ASTE) for use at a subsequent time when a subsequent access register translation (ART) request is made using the same representation of the contents of one of said access register (AR) means; and e. determining from the contents of the general purpose register for containing operands and addresses (GPR) means and the segment table designation (STD) identified in step c. or d., a real address using said virtual address translating means.

Claim 29

Dependent Claim 100 words

Method of claim 26 characterized by storing the access list designation source origin (ALDSO), the access list entry token (ALET), the P bit, the access list entry authorization index (ALEAX), the segment table designation (STD), the extended authorization index (EAX) and the S bit in said ART lookaside buffer (ALB) and wherein said segment table designation (STD) and the authorization to used said segment table designation (STD) is determined by accessing said ART lookaside buffer (ALB) entry using said access list designation source origin (ALDSO) and said access list entry token (ALET) to access said ART lookaside buffer (ALB) entry.

Claim 30

Dependent Claim 318 words

Method of claim 26 characterized by storing the access list designation source origin (ALDSO), the access list entry token (ALET), the private bit, the access list entry authorization index (ALEAX), the ASN second table entry (ASTE) ADR and the ASTE sequence number (ASTESN) in a first indexable table, storing the ASN second table entry (ASTE) address, the ASTE sequence number (ASTESN), the authorization table origin (ATO), the authority table length (ATL) and the segment table designation (STD) in a second indexable table, storing the authorization table origin (ATO), the extended authorization index (EAX) and the S bit in a third indexable table, wherein said ART lookaside buffer (ALB) operates by: using a valid result from the first indexable table to locate an entry in the second indexable table, using a valid result from the second indexable table to locate an entry in the third indexable table and, testing for validity by testing that the following conditions are true: 1. The access list entry token (ALET) to be translated has a value larger than 1. (If the access list entry token (ALET) is 0 or 1, the contents of CR1 or CR7 are used); 2. The access list designation source origin (ALDSO) field in the ALB-ALD/ALE matches the access list designation source origin (ALDSO) being used; 3. The access list entry token (ALET) field in the ALB-ALD/ALE matches the access list entry token (ALET) to be translated; 4. The ALB-ALD/ALE entry passes the access list entry (ALE) authorization test; that is, one of the following conditions is true: a. The private bit in the ALB-ALD/ALE entry is zero; b. The access list entry authorization index (ALEAX) in the ALB-ALD/ALE entry equals the current extended authorization index (EAX); c. The current extended authorization index (EAX) selects a secondary bit(s) that is one for the authority table designated by the ASN second table entry (ASTE) that is addressed by the ALB-ALD/ALE.

Information handling system

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag