Data communication system having channel switching means

Claim 2

A data communication system having a channel switching means (26, 42) for substituting for a main channel a protection channel when a transmission fault occurs in the main channel, both main and protection channels being positioned along respective transmission lines between a transmitter and receiver comprising the data communication system, wherein said receiver contains therein a delay means (27) for delaying in time the data received successively from said transmitter, and said delay means (27) being located along a signal line through which said main channel is formed.

Claim 3

A data communication system as set forth in claim 1, wherein said transmitter contains therein a delay means (43) for delaying in time data sent successively from a data source, which data is to be transmitted to said receiver by way of said protection channel.

Claim 4

A data communication system as set forth in claim 2, wherein said receiver contains therein a detection means (28) for detecting an occurrence of a transmission fault in the main channel, said detection means (28) being located in a preceding stage relative to said receiver side delay means (27) along the flow of the received data.

Claim 5

A data communication system as set forth in claim 3, wherein said detection means (28) sends a command signal, as a switching signal, to said transmitter and activates the transmitter side channel switching means (42) so as to transmit said data sent from the data source to said receiver by way of said transmitter side delay means (43) and through said protection'channel.

Claim 6

A data communication system as set forth in claim 4, wherein said detection means (28) generates an additional switching signal to activate the receiver side channel switching means (26) after a predetermined elapsed time from the detection of said transmission fault so that the received data via the protection channel overlaps with the data delayed by the receiver side delay means (27) during the switching process.

Claim 7

A data communication system as set forth in claim 5, wherein the delay times caused at both the transmitter side and receiver side delay means (43, 27) are set to be substantially the same.

Claim 8

A data communication system as set forth in claim 6, wherein the delay time is defined as a stoppage time of data flow, which stoppage time would be inevitably created by a usual channel switching system, plus a predetermined time margin.

Claim 9

A data communication system as set forth in claim 7, wherein said channel switching means (26) in said receiver is comprised of a synchronous switch circuit (26) which selects the data output from a main channel receiving unit (23) or a protection channel unit (13), and further, said delay means (27) in said receiver is located between the main channel receiving unit (23) and the synchronous switch circuit (26).

Claim 10

A data communication system as set forth in claim 8, wherein said predetermined time margin is defined as being substantially the same as a time required to achieve a phase synchronization in said synchronous switch circuit (26) between the main channel data maintained in said receiver side delay means (27), and the protection channel data maintained in said transmitter side delay means (43), and then transmitted to the synchronous switch circuit (26).

Claim 11

A data communication system as set forth in claim 1, wherein said receiver side delay means (27) is comprised of a shift register (121).

Claim 12

A data communication system as set forth in claim 2, wherein said transmitter side delay means (43) is comprised of a shift register (117).

Claim 13

A data communication system as set forth in claim 5, wherein said detection means (28) is comprised of an integrating circuit (122) which is supplied with the main channel data or the main channel clock, and a comparator (123) which compares in level the output from the integrating circuit (122) and a predetermined reference voltage, to produce from the comparator (123) dai switching signals to be transmitted to said transmitter side channel switching means (42) and also to be applied to said receiver side channel switching means (26).

Claim 14

A data communication system as set forth in claim 8, wherein said synchronous switch circuit (26) is mainly comprised of a protection channel elastic memory (108, 111), a main channel elastic memory (92, 95), a protection channel clock source, a main channel clock source a pattern comparator (114) and switch (100, 115) which produces the selected data, said protection and main channel clock sources supply clocks for activating said protection and main channel elastic memories (108, 111; 92, 95) which momentarily store therein the protection and main channel data received from said transmitter, said pattern comparator (114) compares both the stored data in the protection and main channel elastic memories (108, 111; 92, 95) and if the thus compared data does not match, the pattern comparator (114) inhibits the supply of said clock, bit by bit, until the compared data coincides with each other, and then switches the status of said switch (100, 115) to produce the said selected data.