EP0325856A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Interface circuit for data transfer between processor and input/output device
Assignee: International Business Machines Corp
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Filing: 1988-12-16
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Granted: —
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Expires: 2008-12-16
Abstract
Abstract An interface circuit for transferring data between an input/output device with an n-bit data bus and a processor having an m x n-bit data bus uses a register system to store prefetched data in separate fields from the input/output device along the n-bit data bus for transfer in a single operation to the processor along the m x n-bit data bus and to burst write multiple fields of data from the processor to the register system along the m x n-bit data bus for later transfer of the fields separately to the input/output device along the n-bit data bus.
Inventors
- 👤 James Stanley Pogorzelski
- 👤 Craig Henry Shempert
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 17:59
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
96 words
An interface circuit for transferring data between a processor having an n x m bit processor data bus and an input/output device having an n bit input/output data bus comprising a register system for temporarily storing a group of fields of data and control logic means operable to prefetch a group of said fields, a fields at a time, from the n bit input/output data bus, to store the group in the register system, and to transfer the stored group from the register system to the processor data bus in a single read by the processor.
Claim 2
Dependent Claim
96 words
An interface circuit for transferring data between a processor having an n x m bit processor data bus and an input/output device having an n bit input/output data bus comprising a register system for temporarily storing a group of fields of data and control logic means operable to prefetch a group of said fields, a fields at a time, from the n bit input/output data bus, to store the group in the register system, and to transfer the stored group from the register system to the processor data bus in a single read by the processor.
Claim 3
Dependent Claim
60 words
An interface circuit according to claim 1 in which said control logic is further operable to write a said group of fields of data into said registered system from the processor data bus in a single write operation of the processor, and to transfer the stored group from the processor to the input/output data bus a field at a time.
Claim 4
Dependent Claim
37 words
An interface circuit according to claim 2 in which said control logic is further operable, on reception of a data service request interrupt from the input/output device, to initiate the prefetching of said group from the processor.
Claim 5
Dependent Claim
51 words
An interface circuit according to claim 3, in which said control logic is operable to suspend the prefetching of said group from the processor on receipt of a read request or a write request from the processor and to resume the prefetching on completion of a corresponding read or write operation.
Claim 6
Dependent Claim
34 words
An interface circuit according to any one of the previous claims in which the control logic is operable, in response to a control service request from the input/output device, to generate a processor interrupt.
Claim 7
Independent Claim
76 words
A method of communicating data between an input/output device having an n bit data bus and a processor having an m x n bit data bus, comprising the steps of: prefetching a group of fields, a group at a time, from the input/output device along the n bit data bus; storing said fields in a register system; and transferring said fields, in a single operation, to the processor along the m x n bit data bus.
Claim 8
Independent Claim
76 words
A method of communicating data between an input/output device having an n bit data bus and a processor having an m x n bit data bus, comprising the steps of: prefetching a group of fields, a group at a time, from the input/output device along the n bit data bus; storing said fields in a register system; and transferring said fields, in a single operation, to the processor along the m x n bit data bus.
Claim 9
Dependent Claim
64 words
A method according to claim 6, further comprising the steps of: transferring a group of fields of data simultaneously from the processors to the register system along the m x n data bus; storing the transferred group in the register system; and transferring the group, a field at a time, from the register system to the input/output device along the n bit data bus.
References Cited (Backward Citations)
No citation records indexed.
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