EP0325420A2
Expired / Lapsed
EP
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Organization of an integrated cache unit for flexible usage in cache system design
Assignee: Advanced Micro Devices Inc
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Filing: 1989-01-18
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Granted: —
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Expires: 2009-01-18
Abstract
Abstract Methods and apparatus are disclosed for realizing an integrated cache unit which may be flexibly used for cache system design. The preferred embodiment of the invention comprises both a cache memory and a cache controller on a single chip. In accordance with an alternative embodiment of the invention, the cache memory may be externally located. Flexible cache system design is achieved by the specification of desired cache features through the setting of appropriate cache option bits. The disclosed methods and apparatus support this user oriented approach to flexible system design. The actual setting of option bits may be peformed under software control and allows a high performance cache system to be designed with few parts, at low cost and with the ability to perform with high efficiency.
Inventors
- 👤 Gigy Baror
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 02:03
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/0862; G06F2212/00; G06F2212/60; G06F2212/601
Claims Analysis
Total Claims: 43
Claim 1
Independent Claim
195 words
An integrated cache unit ("ICU") architecture that supports flexible cache system design and implements cache functions in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitate communication between said CPU and the ICU, memory and memory bus means which facilitate communication between said memory and the ICU, comprising: (a) a processor bus unit, coupled to said processor bus means, for controlling an ICU/processor bus interface; (b) a memory bus unit, coupled to said memory bus means, for controlling an ICU/memory bus interface; and (c) a programmable cache unit, coupled to both said processor bus unit, and said memory bus unit, for performing cache functions, wherein said programmable cache unit includes tag array means and valid array means with, in a first configuration, associated memory array means located within said programmable cache unit, and in a second configuration, said associated memory means being located outside said programmable cache unit, and further wherein said tag array means, said valid array means and said memory array means are organized as a 2 n way set associative cache where n is an integer greater than or equal to zero.
Claim 2
Dependent Claim
195 words
An integrated cache unit ("ICU") architecture that supports flexible cache system design and implements cache functions in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitate communication between said CPU and the ICU, memory and memory bus means which facilitate communication between said memory and the ICU, comprising: (a) a processor bus unit, coupled to said processor bus means, for controlling an ICU/processor bus interface; (b) a memory bus unit, coupled to said memory bus means, for controlling an ICU/memory bus interface; and (c) a programmable cache unit, coupled to both said processor bus unit, and said memory bus unit, for performing cache functions, wherein said programmable cache unit includes tag array means and valid array means with, in a first configuration, associated memory array means located within said programmable cache unit, and in a second configuration, said associated memory means being located outside said programmable cache unit, and further wherein said tag array means, said valid array means and said memory array means are organized as a 2 n way set associative cache where n is an integer greater than or equal to zero.
Claim 3
Dependent Claim
38 words
An ICU architecture as set forth in claim 1 wherein said memory array means stores cached data and instruction signals and is organized as a set of blocks, each block corresponding to a predetermined number of cached words.
Claim 4
Dependent Claim
23 words
An ICU architecture as set forth in claim 2 wherein each block has at least one associated tag stored in said tag array.
Claim 5
Dependent Claim
24 words
An ICU architecture as set forth in claim 3 wherein each block has at least one associated validity bit stored in said valid array.
Claim 6
Dependent Claim
20 words
An ICU architecture as set forth in claim 4 wherein said programmable cache unit supports variable block and sub-block sizing.
Claim 7
Dependent Claim
18 words
An ICU architecture as set forth in claim 4 wherein said programmable ICU supports flexible reloading cache operations.
Claim 8
Dependent Claim
128 words
An ICU architecture as set forth in claim 4 wherein said processor bus unit further comprises: (a) first address incrementer means, coupled to said processor bus means and said programmable cache unit, for receiving, latching and incrementing address signals input from said processor bus means and for outputting address signals to said programmable cache unit to facilitate cache accesses; (b) data shifter means, coupled to said processor bus means and said programmable cache unit, for aligning data signals input from said processor bus means and for aligning data signals output by said programmable cache unit for transmission to said processor; and (c) processor bus unit control means, for synchronizing and controlling the operation of said first address incrementer means, said data shifter means and said programmable cache unit.
Claim 9
Dependent Claim
164 words
An ICU architecture as set forth in claim 4 wherein said memory bus unit further comprises: (a) a selectively enabled write buffer for buffering address and data signals being transmitted between said memory bus means and said programmable cache means; (b) memory address logic means, coupled to said memory bus means, said write buffer and said programmable cache unit, for latching and incrementing memory bus addresses input over said memory bus means and for latching and incrementing addresses for cache read operations initiated by said programmable cache means; (c) memory read buffer means, coupled to said memory bus means, said write buffer and said programmable cache means, for buffering data from said memory bus means until said programmable cache means is available for update and for supporting both prefetch and read operations; and (d) memory bus unit control means, for synchronizing and controlling the operation of said write buffer, said memory address logic means, said memory read buffer means, and said programmable cache unit.
Claim 10
Dependent Claim
22 words
An ICU architecture as set forth in claim 8 wherein said write buffer further comprises an address buffer and a data buffer.
Claim 11
Dependent Claim
153 words
An ICU architecture as set forth in claim 4 wherein said programmable cache unit further comprises: (a) a cache unit address bus, coupled to said processor bus unit and said memory bus unit, for carrying address signals; (b) a cache unit data bus, coupled to said processor bus unit and said memory bus unit, for carrying data signals; (c) block status array means coupled to said cache data bus, for storing an indication of the modified, shared and locked status of each block; (d) a set of special registers, coupled to said cache unit address bus and said cache unit data bus, for selecting programmable options, supporting cache control operations and indicating cache status information; and (e) cache unit control means, coupled to said processor bus control means and said memory bus control means, for synchronizing and controlling operations of said programmable cache unit, said processor bus unit and said memory bus unit.
Claim 12
Dependent Claim
44 words
An ICU architecture as set forth in claim 10 wherein said cache control means further comprises logic means, coupled to said cache unit address bus and said tag array, for comparing addresses on said cache unit address bus with tags in said tag array.
Claim 13
Dependent Claim
39 words
An ICU architecture as set forth in claim 11 wherein said cache control means further comprises logic means, coupled to said valid array, for determining if a particular cached word is valid at the time of a cache access.
Claim 14
Dependent Claim
42 words
An ICU architecture as set forth in claim 12 wherein said cache control means is further operative to generate hit signals for valid cache accesses and maintains and updates data stored in said set of special registers and said block status array.
Claim 15
Dependent Claim
33 words
An ICU architecture as set forth in claim 10 further comprising least recently used (LRU) array means for storing LRU bits whenever an LRU replacement algorithm is utilized by said programmable cache unit.
Claim 16
Dependent Claim
33 words
An ICU architecture as set forth in claim 10 wherein said set of special registers further comprises at least one programmable register for storing signals indicative of user selected ICU options and policies.
Claim 17
Dependent Claim
22 words
An ICU architecture as set forth in claim 15 further comprising means for supporting flexible multiprocessor operations and assuring cache data consistency.
Claim 18
Dependent Claim
20 words
An ICU architecture as set forth in claim 15 that is integrated on a single chip, is modular and expandable.
Claim 19
Dependent Claim
31 words
An ICU architecture as set forth in claim 15 wherein said set of special registers includes at least one programmable register having at least one bit for disabling a read-through option.
Claim 20
Dependent Claim
32 words
An ICU architecture as set forth in claim 15 wherein said set of special registers includes at least one programmable register having at least one bit for enabling a single access prefetch.
Claim 21
Dependent Claim
31 words
An ICU architecture as set forth in claim 16 wherein said set of special registers includes at least one programmable register having at least one bit for disabling wrap around addressing.
Claim 22
Dependent Claim
38 words
An ICU architecture as set forth in claim 15 wherein said set of special registers includes at least one programmable register having at least one bit for controlling the operation of the ICU on a single access miss.
Claim 23
Dependent Claim
43 words
An ICU architecture as set forth in claim 15 wherein said set of special registers includes at least one programmable register having at least one bit for controlling the operation of the ICU when a burst-mode read request is terminated by the processor.
Claim 24
Dependent Claim
33 words
An ICU architecture as set forth in claim 15 wherein said set of special registers includes at least one programmable register having at least one bit for enabling a prefetch option in burst-mode.
Claim 25
Dependent Claim
32 words
An ICU architecture as set forth in claim 15 wherein said set of special registers includes at least one programmable register having at least one bit for specifying and varying sub-block size.
Claim 26
Dependent Claim
32 words
An ICU architecture as set forth in claim 15 wherein said set of special registers includes at least one programmable register having at least one bit for selecting a write allocate option.
Claim 27
Dependent Claim
35 words
An ICU architecture as set forth in claim 15 wherein said set of special registers includes at least one programmable register having at least one bit for selecting write policy options on a global basis.
Claim 28
Dependent Claim
31 words
An ICU architecture as set forth in claim 15 wherein said set of special registers includes at least one programmable register having at least one bit for specifying block replacement policy.
Claim 29
Dependent Claim
36 words
An ICU architecture as set forth in claim 15 wherein said set of special registers includes at least one programmable register having at least one bit for selecting a 2 n way set associative cache organization.
Claim 30
Dependent Claim
49 words
An ICU architecture as set forth in claim 15 wherein said set of special registers includes at least one programmable register having at least one bit for specifying cache operation as an instruction cache in a first mode and specifying cache operation as data cache in a second mode.
Claim 31
Dependent Claim
27 words
An ICU architecture as set forth in claim 26 further comprising means for supporting user specified, write-through and copy-back write policies on a flexible per access basis.
Claim 32
Dependent Claim
33 words
An ICU architecture as set forth in claim 15 wherein said CPU is a simplified instruction processor having burst and pipelined protocols and further wherein said ICU comprises means for supporting said protocols.
Claim 33
Dependent Claim
23 words
An ICU architecture as set forth in claim 15 further comprising fault tolerance support means including means for generating and checking byte parity.
Claim 34
Dependent Claim
31 words
An ICU architecture is set forth in claim 28 wherein said fault tolerance support means further comprises means for operating said ICU in a cache master and a cache slave mode.
Claim 35
Dependent Claim
29 words
An ICU architecture as set forth in claim 15 supporting the preloading of instructions and data into said cache memory before the start of program execution by said processor.
Claim 36
Independent Claim
209 words
A method for flexibly designing an integrated cache unit ("ICU") architecture that implements cache functions in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitate communication between said CPU and the ICU, memory and memory bus means which facilitate communication between said memory and the ICU, comprising the steps of: (a) controlling an ICU/processor bus interface from within said ICU utilizing a processor bus unit coupled to said processor bus means; (b) controlling an ICU/memory bus interface from within said ICU utilizing a memory bus unit coupled to said memory bus means; and (c) performing cache functions from within said ICU utilizing a programmable cache unit coupled to both said processor bus unit and said memory bus unit, wherein said programmable cache unit includes tag array means and valid array means with, in a first configuration, associated memory array means located within said programmable cache unit, and in a second configuration, said associated memory means being located outside said programmable cache unit, and further wherein said tag array means, said valid array means and said memory array means are organized as a 2 n way set associative cache where n is an integer greater than or equal to zero.
Claim 37
Independent Claim
209 words
A method for flexibly designing an integrated cache unit ("ICU") architecture that implements cache functions in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitate communication between said CPU and the ICU, memory and memory bus means which facilitate communication between said memory and the ICU, comprising the steps of: (a) controlling an ICU/processor bus interface from within said ICU utilizing a processor bus unit coupled to said processor bus means; (b) controlling an ICU/memory bus interface from within said ICU utilizing a memory bus unit coupled to said memory bus means; and (c) performing cache functions from within said ICU utilizing a programmable cache unit coupled to both said processor bus unit and said memory bus unit, wherein said programmable cache unit includes tag array means and valid array means with, in a first configuration, associated memory array means located within said programmable cache unit, and in a second configuration, said associated memory means being located outside said programmable cache unit, and further wherein said tag array means, said valid array means and said memory array means are organized as a 2 n way set associative cache where n is an integer greater than or equal to zero.
Claim 38
Dependent Claim
33 words
A method as set forth in claim 35 further comprising the step of organizaing said memory array means as a set of blocks, each block corresponding to a predetermined number of cached words.
Claim 39
Dependent Claim
142 words
A method as set forth in claim 36 wherein the step of controlling said ICU/processor bus interface further comprises the steps of: (a) receiving, latching and incrementing address signals input from said processor bus means utilizing first address incrementer means coupled to said processor bus means and said programmable cache unit; (b) outputting address signals from said first incrementer means to said programmable cache unit to facilitate cache accesses; (c) aligning data signals input from said processor bus means utilizing data shifter means coupled to said processor bus means and said programmable cache unit; (d) aligning data signals output by said programmable cache unit for transmission to said processor via said data shifter means; and (e) synchronizing and controlling the operation of said first address incrementer means, said data shifter means and said programmable cache unit via processor bus unit control means.
Claim 40
Dependent Claim
166 words
A method as set forth in claim 36 wherein the step of controlling said ICU/memory bus interface further comprises the steps of: (a) buffering address and data signals being transmitted between said memory bus means and said programmable cache means in a selectively enabled write buffer; (b) latching and incrementing memory bus addresses input over said memory bus means utilizing memory address logic means, coupled to said memory bus means, said write buffer and said programmable cache unit; (c) latching and incrementing addresses for cache read operations initiated by said programmable cache means utilizing said memory address logic means; (d) buffering data from said memory bus means utilizing memory read buffer means coupled to said memory bus means, said write buffer and said programmable cache means, until said programmable cache means is available for update; (e) synchronizing and controlling the operation of said write buffer, said memory address logic means, said memory read buffer means, and said programmable cache unit via memory bus unit control means.
Claim 41
Dependent Claim
210 words
A method as set forth in claim 36 wherein said step of performing cache functions utilizing a programmable cache unit further comprises the steps of: (a) carrying address signals within said ICU on an internal cache unit address bus coupled to said processor bus unit and said memory bus unit; (b) carrying data signals within said ICU on an internal cache unit data bus coupled to said processor bus unit and said memory bus unit; (c) storing data and instruction signals to be cached, in said memory array means; (d) storing cache tags in said tag array means, wherein each tag corresponds to a block of a predetermined number of cached words; (e) storing data pertaining to the validity of each cached word in said valid array means; (f) storing an indication of the modified, shared and locked status of each block in block status array means coupled to said cache data bus; (g) utilizing a set for special registers, coupled to said cache unit address bus and said cache unit data bus, for selecting programmable options, supporting cache control operations and indicating cache status information; and (h) synchronizing and controlling operations of said programmable cache unit, said processor bus and said memory bus unit via cache unit control means.
Claim 42
Dependent Claim
77 words
A method as set forth in claim 39 wherein said step of synchronizing and controlling further comprises the steps of: (a) comparing addresses on said cache unit address bus with tags in said tag array; (b) determining if a particular cached word is valid at the time of a cache access; (c) generating hit signals for valid cache accesses; and (d) maintaining and updating data stored in said set of special registers and said block status array.
Claim 43
Dependent Claim
33 words
A method as set forth in claim 39 further comprising the step of storing signals indicative of user selected ICU options and policies in at least one of said set of special registers.
References Cited (Backward Citations)
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