Semiconductor memory circuit with improved serial access circuit arrangement

Claim 2

A semiconductor memory circuit comprising first and second memory planes, each of said first and second memory planes including first and second memory arrays, each of said first and second memory arrays having a plurality of word lines, a plurality of bit lines intersecting with said word lines and a plurality of memory cells coupled to the word lines and the bit lines; a data hold circuit having a plurality of latch circuits each having an input end and an output end; a first data transfer circuit connected between the bit lines of said first memory array and the input ends of said latch circuits of said data hold circuit; a second data transfer circuit connected between the digit lines of said second memory array and the input ends of said latch circuits of said data hold circuit; and a means for serially outputting the data held in said latch circuits; and said semiconductor memory circuit further comprising first means for operatively enabling first transfer circuits of said first and second memory planes simultaneously thereby to transfer data on the bit lines of the first memory arrays of said first and second memory planes to said data hold circuits of said first and second memory planes, respectively.

Claim 3

The memory circuit according to claim 1, wherein said serially outputting means comprises a data output line, a plurality of transfer gates connected between the respective output ends of said latch circuit and said data output line, and a serial selection circuit coupled to said plurality of transfer gates for sequentially enabling said transfer gates to close to transfer the data held in said latch circuit to said data output line.

Claim 4

The memory circuit according to claim 1, in which each of said first and second memory planes further includes first and second random data lines, a plurality of first selection transistors connected between said first random data line and the bit lines of the first memory array thereof, a plurality of second selection transistors connected between said second random data line and the bit lines of the second memory array thereof, and a random selection circuit for operatively enabling one of said first selection transistors and one of said second selection transistors.

Claim 5

The memory circuit according to claim 1, in which each of said first and second memory arrays further includes a plurality of sense amplifiers provided for the digit lines thereof.

Claim 6

The memory circuit according to claim 1, in which each of said memory cells is of a dynamic type.

Claim 7

A semiconductor memory circuit comprising first and second memory arrays, each of said first and second memory arrays including word lines arranged in rows, bit lines arranged in columns and intersecting said word lines, and a plurality of memory cells formed at the intersecting of said bit and word lines; a first row decoder for operatively selecting one of the word lines of said first memory array; a second row decoder for operatively selecting one of the word lines of said second memory array; first means for enabling one of said first and second row decoders; a data hold circuit having a plurality of latch circuits each having an input end and an output end; a plurality of first data transfer means connected between the input ends of said latch circuits and the bit lines of said first memory arrays for operatively transferring data at the digit lines of said first memory array to the input ends of said latch circuits; a plurality of second data transfer means connected between the input ends of said latch circuits and the bit lines of said second memory array for operatively transferring data at the bit lines of said second memory array to the input ends of said latch circuits; first control means for operatively enabling said first data transfer means when said first row decoder is enabled; and second control means for operatively enabling said second data transfer means when said second row decoder is enabled; and a means for serially outputting the data held in said latch circuits.

Claim 8

A semiconductor memory circuit comprising first and second memory arrays, each of said first and second memory arrays including word lines arranged in rows, bit lines arranged in columns and intersecting said word lines, and a plurality of memory cells formed at the intersecting of said bit and word lines; a first row decoder for operatively selecting one of the word lines of said first memory array; a second row decoder for operatively selecting one of the word lines of said second memory array; first means for enabling one of said first and second row decoders; a data hold circuit having a plurality of latch circuits each having an input end and an output end; a plurality of first data transfer means connected between the input ends of said latch circuits and the bit lines of said first memory arrays for operatively transferring data at the digit lines of said first memory array to the input ends of said latch circuits; a plurality of second data transfer means connected between the input ends of said latch circuits and the bit lines of said second memory array for operatively transferring data at the bit lines of said second memory array to the input ends of said latch circuits; first control means for operatively enabling said first data transfer means when said first row decoder is enabled; and second control means for operatively enabling said second data transfer means when said second row decoder is enabled; and a means for serially outputting the data held in said latch circuits.

Claim 9

The semiconductor memory circuit according to claim 6, in which said serially outputting means comprises a serial data line, a plurality of third data transfer means connected between said serial data line and the output ends of said latch circuits; and a serial selection circuit for sequentially enabling said third data transfer means one by one.

Claim 10

The semiconductor memory circuit according to claim 6, further comprising a first random access port for operatively deriving data at one of the bit lines of said first memory array and a second random access port for operatively deriving data at one of the bit lines of said second memory array.