EP0323896A2
Expired / Lapsed
EP
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Complementary semiconductor device
Assignee: Fujitsu Ltd
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Filing: 1989-01-05
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Granted: —
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Expires: 2009-01-05
Abstract
Abstract A complementary semiconductor device (CMOS gate) including a p-channel transistor (PMOS FET) and an n-channel transistor (NMOS FET) comprises: a silicon substrate (1); a channel layer (2) for the p-channel transistor which comprises a first Si 1-x Ge x layer (2A), a Ge layer (2B), and a second Si 1-x Ge x layer (2C) formed in sequence on the silicon substrate (1); and a silicon layer (3) as another channel layer for the n-channel transistor formed on the channel layer. The ratio "x" of the first Si 1-x Ge x layer (2A) is continuously increased from 0 to 1, and the ration "x" of the second Si 1-x Ge x layer (2B) is continuously decreased from 1 to 0.
Inventors
- 👤 Yuji Awano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 03:07
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/82; H10D62/822; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/60; H10D30/751; H10D30/80; H10D30/801; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/0165; H10D84/0167; H10D84/0193; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
68 words
A complementary semiconductor device including a p-channel transistor and an n-channel transistor comprising: a silicon substrate; a channel layer for the p-channel transistor which comprises a first Si 1-x Ge x layer, a Ge layer, and a second Si 1-x Ge x layer formed in sequence on said silicon substrate; and a silicon layer as another channel layer for the n-channel transistor being formed on said channel layer.
Claim 2
Dependent Claim
68 words
A complementary semiconductor device including a p-channel transistor and an n-channel transistor comprising: a silicon substrate; a channel layer for the p-channel transistor which comprises a first Si 1-x Ge x layer, a Ge layer, and a second Si 1-x Ge x layer formed in sequence on said silicon substrate; and a silicon layer as another channel layer for the n-channel transistor being formed on said channel layer.
Claim 3
Dependent Claim
26 words
A complementary semiconductor device according to claim 1, wherein the ratio "x" of said first Si 1-x Ge x layer continuously varies from 0 to 1.
Claim 4
Dependent Claim
28 words
A complementary semiconductor device according to claim 1 or 2, wherein the ratio "x" of said second Si 1-x Ge x layer continuously varies from 1 to 0.
Claim 5
Dependent Claim
26 words
A complementary semiconductor device according to claim 1, 2 or 3, wherein said Ge layer consists of from 90 to 100% Ge and the rest Si.
Claim 6
Dependent Claim
31 words
A complementary semiconductor device according to claim 1, 2, 3 or 4, wherein said silicon substrate is i-type or p-type, said Ge layer is p-type, and said silicon layer is p-type.
Claim 7
Dependent Claim
19 words
A complementary semiconductor device according to claim 5, wherein said first and second SiGe layers are p-type or i-type.
Claim 8
Dependent Claim
29 words
A complementary semiconductor device according to claim 1, 2, 3 or 4 wherein said silicon substrate, first SiGe layer, Ge layer, second SiGe layer, and silicon layer are i-type.
Claim 9
Dependent Claim
95 words
A complementary semiconductor device according to any preceding claim, further comprising a source region and a drain region of said p-channel transistor which are formed by doping p-type impurities to said silicon substrate through the silicon layer and the channel layer, another source region and another drain region of said n-channel transistor which are formed by doping n-type impurities to said channel layer through the silicon layer, and an isolation region isolating said p-channel transistor and n-channel transistor from each other and extending to said silicon substrate through said silicon layer and said channel layer.
Claim 10
Dependent Claim
52 words
A complementary semiconductor device according to claim 8, wherein a gate insulating layer and a gate electrode formed thereon are formed on said silicon layer between said source and drain regions for said p-channel transistor, and a source electrode and a drain electrode come into contact with said source and drain regions.
Claim 11
Dependent Claim
54 words
A complementary semiconductor device according to claim 8, wherein a gate insulating layer and a gate electrode formed thereon are formed on said silicon layer between said another source and drain regions for said n-channel transistor, and a source electrode and a drain electrode come into contact with said another source and drain regions.
Claim 12
Dependent Claim
14 words
A complementary semiconductor device according to any preceding claim, forming a CMOS inverter gate.
Claim 13
Dependent Claim
134 words
A complementary semiconductor device including a p-channel transistor and an n-channel transistor comprising; a silicon substrate having a first region and a second region at a surface thereof; a channel layer for the p-channel transistor which comprises a first Si 1-x Ge x layer, a Ge layer, and a second Si 1-x Ge x layer formed in sequence on said first and second region; a silicon layer as another channel layer for the n-channel transistor being formed on said channel layer over said first and second region; a first gate insulating layer and a first gate electrode formed on said silicon layer above said first region for the p-channel transistor; and a second gate insulating layer and a second gate electrode formed on said silicon layer above said second region fo the n-channel transistor.
Claim 14
Dependent Claim
134 words
A complementary semiconductor device including a p-channel transistor and an n-channel transistor comprising; a silicon substrate having a first region and a second region at a surface thereof; a channel layer for the p-channel transistor which comprises a first Si 1-x Ge x layer, a Ge layer, and a second Si 1-x Ge x layer formed in sequence on said first and second region; a silicon layer as another channel layer for the n-channel transistor being formed on said channel layer over said first and second region; a first gate insulating layer and a first gate electrode formed on said silicon layer above said first region for the p-channel transistor; and a second gate insulating layer and a second gate electrode formed on said silicon layer above said second region fo the n-channel transistor.
References Cited (Backward Citations)
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