EP0323156A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Voltage multiplier circuit
Assignee: Waferscale Integration Inc
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Filing: 1988-12-22
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Granted: —
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Expires: 2008-12-22
Abstract
Abstract An EEPROM includes a voltage multiplier (100) for generating an erase voltage and a voltage regulator circuit (108) for controlling the magnitude of the erase voltage. The voltage regulator circuit includes means for providing a first voltage proportional to the erase voltage, means for providing a reference voltage on a reference voltage lead, and means for controlling the voltage multiplier circuit so that if the first voltage is less than the reference voltage, the voltage multiplier circuit will increase the erase voltage, but if the first voltage is greater than the reference voltage, the voltage multiplier will not continue to increase the erase voltage. The voltage multiplier (100) includes capacitors (103) and transistors (101;105) constructed using standard EEPROM processing to withstand high voltages without breaking down.
Inventors
- 👤 Reza Kazerounian
- 👤 Syed Ali
- 👤 Boaz Eitan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 14:50
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/30; H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M3/073; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/49; H10B69/00
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
261 words
A structure including a first region of semiconductor material of a first conductivity type, a second region of a second conductivity type formed in the first region, a third region of the second conductivity type formed in the first region and spaced apart from the second region, one of the second and third regions serving as a first source region, the other of the second and third regions serving as a first drain region, a first channel region extending between the first source region and the first drain region, a first insulating layer formed above the first insulating layer, a second insulating layer formed above the floating gate, a control gate formed above the second insulating layer, the first drain, the first source, the floating gate and the control gate serving as a first transistor, a fourth region of a second conductivity type formed in the first region, a second source region of the first conductivity type formed in the fourth region, a second drain region of the first conductivity type formed in the fourth region and spaced apart from the second source region, and a third gate formed above but insulated from the fourth region, the third gate, the second source region, and the second drain region serving as a second transistor, characterized in that at least the second region extends to a depth substantially equal to the depth of the fourth region so that the breakdown voltage of the junction between the first and second regions is approximately equal to the breakdown voltage between the first and fourth regions.
Claim 2
Dependent Claim
261 words
A structure including a first region of semiconductor material of a first conductivity type, a second region of a second conductivity type formed in the first region, a third region of the second conductivity type formed in the first region and spaced apart from the second region, one of the second and third regions serving as a first source region, the other of the second and third regions serving as a first drain region, a first channel region extending between the first source region and the first drain region, a first insulating layer formed above the first insulating layer, a second insulating layer formed above the floating gate, a control gate formed above the second insulating layer, the first drain, the first source, the floating gate and the control gate serving as a first transistor, a fourth region of a second conductivity type formed in the first region, a second source region of the first conductivity type formed in the fourth region, a second drain region of the first conductivity type formed in the fourth region and spaced apart from the second source region, and a third gate formed above but insulated from the fourth region, the third gate, the second source region, and the second drain region serving as a second transistor, characterized in that at least the second region extends to a depth substantially equal to the depth of the fourth region so that the breakdown voltage of the junction between the first and second regions is approximately equal to the breakdown voltage between the first and fourth regions.
Claim 3
Dependent Claim
19 words
A structure as claimed in Claim 1 characterized in that the second transistor is part of a CMOS circuit.
Claim 4
Dependent Claim
74 words
A structure as claimed in Claim 1 or 2 characterized by a field insulating layer thicker than the first and second insulating layers formed above a portion of the first region, the floating and control gates and the second insulating layer extending over the field insulating layer adjusts the capacitive coupling between the floating and control gates to thereby increase the breakdown voltage between the control gate and the rest of the first transistor.
Claim 5
Dependent Claim
33 words
A structure as claimed in Claim 3 characterized in that the portion of the control gate not extending over the field insulating layer is laterally surrounded by a portion of the floating gate.
Claim 6
Dependent Claim
165 words
A structure as claimed in Claim 1 or 2 characterized by a plurality of floating gate memory cell transistors having sources, drains and channel regions formed in the first region, wherein the dopant concentration in the first channel region is less than the dopant concentration in the channel regions of the plurality of floating gate memory cell transistors, wherein the first source region comprises a first N+ region formed in a first N- region and the first drain region comprises a second N+ region formed in a second N- region, wherein the distance between the first and second N+ regions is at least twice the length of the channel regions of the plurality of floating gate memory cell transistors, and wherein the low channel dopant concentration in the first transistor, the long distance of separation between the first and second N+ regions, and the presence of the first and second N- regions cooperate to prevent the floating gate of the first transistor from being programmed.
Claim 7
Dependent Claim
87 words
A capacitor comprising a first region of semiconductor material of a first conductivity type and a second region of semiconductor material of a second conductivity type opposite the first conductivity type formed within the first region, the second region serving as a first plate of the capacitor, characterized by: a first conductive layer formed above but insulated from the second region; and a second conductive layer formed above but insulated from the first conductive layer, the second conductive layer serving as a second plate of said capacitor.
Claim 8
Dependent Claim
87 words
A capacitor comprising a first region of semiconductor material of a first conductivity type and a second region of semiconductor material of a second conductivity type opposite the first conductivity type formed within the first region, the second region serving as a first plate of the capacitor, characterized by: a first conductive layer formed above but insulated from the second region; and a second conductive layer formed above but insulated from the first conductive layer, the second conductive layer serving as a second plate of said capacitor.
Claim 9
Dependent Claim
86 words
A capacitor as claimed in Claim 6 wherein the capacitor is part of a circuit characterized by: a third region of the second conductivity type formed within the first region, the second region extending to substantially the same depth as the third region; a source region of the first conductivity type formed within the third region; a drain region of the first conductivity type formed within the third region, a channel extending between the source and drain regions; and a gate formed above the channel region.
Claim 10
Dependent Claim
92 words
A capacitor characterized by a first insulating layer; a first conductive layer formed on the first insulating layer; a second insulating layer formed on the first conductive layer; a second conductive layer formed on a first proportion of the second insulating layer but not on a second portion of the second insulating layer, the second conductive layer serving as a first plate of said capacitor; and a third conductive layer formed on the second portion of the second insulating layer, the third conductive layer serving as a second plate of the capacitor.
Claim 11
Dependent Claim
92 words
A capacitor characterized by a first insulating layer; a first conductive layer formed on the first insulating layer; a second insulating layer formed on the first conductive layer; a second conductive layer formed on a first proportion of the second insulating layer but not on a second portion of the second insulating layer, the second conductive layer serving as a first plate of said capacitor; and a third conductive layer formed on the second portion of the second insulating layer, the third conductive layer serving as a second plate of the capacitor.
Claim 12
Dependent Claim
22 words
A capacitor as claimed in Claim 8 characterized in that the capacitor is part of a voltage multiplier in an integrated circuit.
Claim 13
Dependent Claim
26 words
A capacitor as claimed in Claim 8 or 9 characterized in that the first insulating layer is part of the field insulation of an integrated circuit.
Claim 14
Dependent Claim
169 words
A structure comprising a voltage multiplier, the voltage multiplier comprising a plurality of transistors coupled in series between an input lead and an output lead, each transistor within the plurality of transistors comprising a source region, a drain region, a channel region extending between the source region and the drain region, and a first insulating layer formed over the first channel region,the plurality of transistors being characterised by: a floating gate formed over the first insulating layer; a second insulating layer formed over the floating gate; and a control gate formed over the second insulating layer, the control gate being connected to the drain region, and wherein the voltage multiplier comprises a plurality of capacitors, each capacitor having a first plate coupled to the control gate of an associated one of the transistors, a first group of capacitors within the plurality of capacitors having a second plate receiving a clock signal φ, and a second group of capacitors within the plurality of capacitors receiving a clock signal φ .
Claim 15
Dependent Claim
169 words
A structure comprising a voltage multiplier, the voltage multiplier comprising a plurality of transistors coupled in series between an input lead and an output lead, each transistor within the plurality of transistors comprising a source region, a drain region, a channel region extending between the source region and the drain region, and a first insulating layer formed over the first channel region,the plurality of transistors being characterised by: a floating gate formed over the first insulating layer; a second insulating layer formed over the floating gate; and a control gate formed over the second insulating layer, the control gate being connected to the drain region, and wherein the voltage multiplier comprises a plurality of capacitors, each capacitor having a first plate coupled to the control gate of an associated one of the transistors, a first group of capacitors within the plurality of capacitors having a second plate receiving a clock signal φ, and a second group of capacitors within the plurality of capacitors receiving a clock signal φ .
Claim 16
Dependent Claim
82 words
A structure as claimed in Claim 11 characterized in that each of the capacitors comprises: a first conductive layer formed on a third insulating layer; a fourth insulating layer formed on the first conductive layer; a second conductive layer formed over a first portion of the fourth insulating layer, the second conductive layer serving as the first plate; and a third conductive layer formed over a second portion of the fourth insulating layer, the third conductive layer serving as the second plate.
Claim 17
Dependent Claim
54 words
A structure as claimed in Claim 11 or 12 characterized in that the voltage multiplier is part of a semiconductor wafer comprising a second plurality of transistors, the drain-substrate and source-substrate breakdown voltage of the first plurality of transistors being greater than the drain-substrate and source-substrate breakdown voltage of said second plurality of transistors.
Claim 18
Dependent Claim
41 words
A structure as claimed in Claim 13 characterized in that the drain-substrate and source-substrate breakdown voltage of the first plurality of transistors exceeds the drain-substrate and source- substrate breakdown voltage of the second plurality of transistors by at least 5 volts.
Claim 19
Dependent Claim
93 words
An integrated circuit including a voltage regulator comprising an input terminal for receiving an input voltage, an output terminal for providing an output voltage, and voltage means for generating the output voltage from the input voltage, characterized by: means for receiving a digital value; means for providing a reference voltage of a magnitude responsive to the digital value; and means for comparing said output voltage to the reference voltage and generating a regulator output signal in response thereto, said voltage means adjusting the said output voltage in response to the regulator output signal.
Claim 20
Dependent Claim
93 words
An integrated circuit including a voltage regulator comprising an input terminal for receiving an input voltage, an output terminal for providing an output voltage, and voltage means for generating the output voltage from the input voltage, characterized by: means for receiving a digital value; means for providing a reference voltage of a magnitude responsive to the digital value; and means for comparing said output voltage to the reference voltage and generating a regulator output signal in response thereto, said voltage means adjusting the said output voltage in response to the regulator output signal.
Claim 21
Dependent Claim
35 words
A circuit as claimed in Claim 15 characterized by an array of floating gate memory cells, and means for applying the output voltage to the memory cells to change data stored in the memory cells.
Claim 22
Dependent Claim
109 words
An integrated circuit including a voltage multiplier comprising an input terminal for receiving an input voltage, an output terminal, a clock lead for receiving clock pulses, and means for generating an output voltage on the output terminal from the input voltage in response to the clock pulses, characterized in that the voltage multiplier comprises: means for providing a sense voltage having a magnitude responsive to said output voltage; and means for comparing said sense voltage with a reference voltage, said means for comparing supplying said clock signals to said clock lead when said reference voltage exceeds said sense voltage but not when said sense voltage exceeds said reference voltage.
Claim 23
Dependent Claim
109 words
An integrated circuit including a voltage multiplier comprising an input terminal for receiving an input voltage, an output terminal, a clock lead for receiving clock pulses, and means for generating an output voltage on the output terminal from the input voltage in response to the clock pulses, characterized in that the voltage multiplier comprises: means for providing a sense voltage having a magnitude responsive to said output voltage; and means for comparing said sense voltage with a reference voltage, said means for comparing supplying said clock signals to said clock lead when said reference voltage exceeds said sense voltage but not when said sense voltage exceeds said reference voltage.
Claim 24
Dependent Claim
106 words
A circuit as claimed in Claim 17 characterized in that the means for generating comprises a plurality of transistors coupled in series between the input terminal and the output terminal, the gate of each transistor being connected to its associated drain, and a plurality of capacitors, each capacitor having a first plate coupled to the gate of an associated one of the transistors and a second plate, the second plate of a first group of capacitors within the plurality of capacitors receiving a clock signal φ , the second plate of a second group of capacitors within the plurality of capacitors receiving a clock signal φ.
Claim 25
Dependent Claim
109 words
An integrated circuit including a voltage supply comprising first means for providing an output on an output lead, characterized by a first lead for receiving a first voltage; a plurality of capacitors coupled in series between the output lead and the first lead, the plurality of capacitors serving as a voltage divider; a second lead coupled to a node between two of the capacitors within the plurality, the second lead providing a sense voltage responsive to the output voltage; and second means for providing a reference voltage, the first means comprising means for comparing the sense voltage and the reference voltage and adjusting the output voltage in response thereto.
Claim 26
Dependent Claim
109 words
An integrated circuit including a voltage supply comprising first means for providing an output on an output lead, characterized by a first lead for receiving a first voltage; a plurality of capacitors coupled in series between the output lead and the first lead, the plurality of capacitors serving as a voltage divider; a second lead coupled to a node between two of the capacitors within the plurality, the second lead providing a sense voltage responsive to the output voltage; and second means for providing a reference voltage, the first means comprising means for comparing the sense voltage and the reference voltage and adjusting the output voltage in response thereto.
Claim 27
Dependent Claim
227 words
A circuit as claimed in Claim 19 characterized in at the plurality capacitors comprises: an insulating layer; a first plurality of conductive layers formed over the first insulating layer, each conductive layer within the first plurality serving as a plate of at least one of the capacitors within the plurality of capacitors; a second plurality of conductive layers, a first one of the conductive layers within the second plurality serving as a first plate of a first capacitor within the plurality of capacitors and being formed over but insulated from a first portion of a first conductive layer within the first plurality, the first conductive layer within the first plurality serving as the second plate of the first capacitor and a first plate of a second capacitor within the plurality of capacitors, a second conductive layer within the second plurality of conductive layers being formed over a second portion of the first conductive layer within the first plurality and serving as a second plate of the second capacitor, the second conductive layer within the second plurality extending over but being insulated from at least a portion of a second conductive layer within the first plurality and serving as a first plate of a third capacitor within the plurality of capacitors, the second conductible layer within the first plurality serving as a second plate of the third capacitor.
Claim 28
Dependent Claim
206 words
An integrated circuit comprising a voltage multiplier, the voltage multiplier comprising a first input terminal for receiving a first input voltage, an output terminal for providing output voltage, and voltage means for generating the output voltage from the input voltage, characterized in that the voltage multiplier comprises: a second input terminal for receiving a second input voltage; a third input terminal for receiving a third input voltage; a capacitive voltage divider coupled between said second and third input terminals for generating a reference signal on a reference lead in response to the second and third input voltages, the capacitive voltage divider comprising a plurality of capacitors having a first plate coupled to the reference lead; a plurality of switches, each switch having a lead coupled to the second plate of a uniquely associated one of the capacitors, each switch electrically coupling the second plate of the uniquely associated capacitor to either the second input terminal or the third input terminal; means for providing a sense signal having a magnitude responsive to the output voltage; and means for comparing the reference signal and the sense signal and generating therefrom a comparator output signal, the voltage means adjusting the output voltage in response to the comparator output signal.
Claim 29
Dependent Claim
206 words
An integrated circuit comprising a voltage multiplier, the voltage multiplier comprising a first input terminal for receiving a first input voltage, an output terminal for providing output voltage, and voltage means for generating the output voltage from the input voltage, characterized in that the voltage multiplier comprises: a second input terminal for receiving a second input voltage; a third input terminal for receiving a third input voltage; a capacitive voltage divider coupled between said second and third input terminals for generating a reference signal on a reference lead in response to the second and third input voltages, the capacitive voltage divider comprising a plurality of capacitors having a first plate coupled to the reference lead; a plurality of switches, each switch having a lead coupled to the second plate of a uniquely associated one of the capacitors, each switch electrically coupling the second plate of the uniquely associated capacitor to either the second input terminal or the third input terminal; means for providing a sense signal having a magnitude responsive to the output voltage; and means for comparing the reference signal and the sense signal and generating therefrom a comparator output signal, the voltage means adjusting the output voltage in response to the comparator output signal.
Claim 30
Dependent Claim
19 words
A circuit as claimed in Claim 21 characterized in that the first input voltage equals the second input voltage.
Claim 31
Dependent Claim
26 words
A circuit as claimed in Claim 21 or 22 characterized by a register, the state of the switches being determined by data stored in the register.
Claim 32
Dependent Claim
188 words
A voltage multiplier for providing an output voltage on an output lead comprising a transistor for discharging the output lead, the transistor comprising a first region of semiconductor material of a first conductivity type, a second region of semiconductor material of a second conductivity type formed in the first region, the second region being coupled to the output lead, a third region of semiconductor material of the second conductivity type formed within the first region and spaced apart from the second region, and a channel extending between the second and third regions, characterized in that transistor comprises: a floating gate formed over a first portion of the channel region but not a second portion of the channel region; and a control gate extending over the floating gate and the second portion of the channel region, so that if the voltage at the second region rises, and the voltage at the floating gate rises due to capacitive coupling between the floating gate and the second region, an inversion region will not form extending from the second region to the third region independently of the voltage at the control gate.
Claim 33
Dependent Claim
188 words
A voltage multiplier for providing an output voltage on an output lead comprising a transistor for discharging the output lead, the transistor comprising a first region of semiconductor material of a first conductivity type, a second region of semiconductor material of a second conductivity type formed in the first region, the second region being coupled to the output lead, a third region of semiconductor material of the second conductivity type formed within the first region and spaced apart from the second region, and a channel extending between the second and third regions, characterized in that transistor comprises: a floating gate formed over a first portion of the channel region but not a second portion of the channel region; and a control gate extending over the floating gate and the second portion of the channel region, so that if the voltage at the second region rises, and the voltage at the floating gate rises due to capacitive coupling between the floating gate and the second region, an inversion region will not form extending from the second region to the third region independently of the voltage at the control gate.
Claim 34
Dependent Claim
149 words
A voltage multiplier comprising means for providing an output voltage at an output terminal, characterized by: regulator means for controlling the output voltage; a register for storing data, the regulator means controlling the output voltage to a value determined by the stored data, the register comprising a plurality of memory cells, at least one of the memory cells comprising: a first lead for receiving a first voltage; a second lead for receiving a second voltage; a floating gate transistor having a floating gate, the transistor being either on or off depending on the data stored in the floating gate transistor; and switch means coupled in series with the floating gate transistor between the first and second leads, the switch means being open when the floating gate transistor is on, the switch means being closed when the floating gate transistor is off, so that the cell consumes essentially no power.
Claim 35
Dependent Claim
149 words
A voltage multiplier comprising means for providing an output voltage at an output terminal, characterized by: regulator means for controlling the output voltage; a register for storing data, the regulator means controlling the output voltage to a value determined by the stored data, the register comprising a plurality of memory cells, at least one of the memory cells comprising: a first lead for receiving a first voltage; a second lead for receiving a second voltage; a floating gate transistor having a floating gate, the transistor being either on or off depending on the data stored in the floating gate transistor; and switch means coupled in series with the floating gate transistor between the first and second leads, the switch means being open when the floating gate transistor is on, the switch means being closed when the floating gate transistor is off, so that the cell consumes essentially no power.
Claim 36
Dependent Claim
93 words
A memory cell comprising a first lead for receiving a first voltage, a second lead for receiving a second voltage, and a floating gate transistor having a floating gate, the transistor being either on or off depending on the data stored in the floating gate transistor, characterized by: switch means coupled in series with the floating gate transistor between said first and second leads, the switch means being open when the floating gate transistor is on, and closed when the floating gate transistor is off, so that the cell consumes essentially no power.
Claim 37
Dependent Claim
93 words
A memory cell comprising a first lead for receiving a first voltage, a second lead for receiving a second voltage, and a floating gate transistor having a floating gate, the transistor being either on or off depending on the data stored in the floating gate transistor, characterized by: switch means coupled in series with the floating gate transistor between said first and second leads, the switch means being open when the floating gate transistor is on, and closed when the floating gate transistor is off, so that the cell consumes essentially no power.
Claim 38
Independent Claim
149 words
A method of forming an integrated circuit including a high voltage transistor, the method comprising the steps of forming a well region of a first conductivity type in a first region of semiconductor material of a second conductivity type, forming a first source region and a first drain region of the second conductivity type in the well region such that a first channel region extends between the first source region and the first drain region, and forming second and third regions of the first conductivity type in the first region, wherein one of the second and third regions serves as a second drain region, the other of the second and third regions serves as a second source region, and a second channel region extends between the second source region and the second drain region, characterized by forming at least part of the second region concurrently with the well region.
Claim 39
Independent Claim
149 words
A method of forming an integrated circuit including a high voltage transistor, the method comprising the steps of forming a well region of a first conductivity type in a first region of semiconductor material of a second conductivity type, forming a first source region and a first drain region of the second conductivity type in the well region such that a first channel region extends between the first source region and the first drain region, and forming second and third regions of the first conductivity type in the first region, wherein one of the second and third regions serves as a second drain region, the other of the second and third regions serves as a second source region, and a second channel region extends between the second source region and the second drain region, characterized by forming at least part of the second region concurrently with the well region.
Claim 40
Dependent Claim
55 words
A method as claimed in Claim 27 characterized in that the integrated circuit comprises an EEPROM, the second source and drain regions being part of a second transistor comprising a floating gate and a control gate formed concurrently with the floating and control gates of the EEPROM, the transistor being part of a charge pump.
Claim 41
Independent Claim
167 words
A method of forming an integrated circuit including a capacitor, the method comprising the steps of forming a first well region of a first conductivity type in a first region of semiconductor material of a second conductivity type, forming a source and a drain of the second conductivity type within the first well region such that a channel extends between the source and drain, forming in the first region at least one floating gate transistor including a floating gate and a control gate, characterized by the steps of: forming a second well region of the first conductivity type concurrently with the first well region; forming a layer of floating gate material above the second well region but insulated from the second well region concurrently with the floating gate; and forming a layer of control gate material above but insulated from the layer of floating gate material concurrently with the control gate, the second well region and layer of control gate material serving as electrodes of a capacitor.
Claim 42
Independent Claim
167 words
A method of forming an integrated circuit including a capacitor, the method comprising the steps of forming a first well region of a first conductivity type in a first region of semiconductor material of a second conductivity type, forming a source and a drain of the second conductivity type within the first well region such that a channel extends between the source and drain, forming in the first region at least one floating gate transistor including a floating gate and a control gate, characterized by the steps of: forming a second well region of the first conductivity type concurrently with the first well region; forming a layer of floating gate material above the second well region but insulated from the second well region concurrently with the floating gate; and forming a layer of control gate material above but insulated from the layer of floating gate material concurrently with the control gate, the second well region and layer of control gate material serving as electrodes of a capacitor.
Claim 43
Independent Claim
97 words
A method of forming an integrated circuit comprising field oxide regions, and a plurality of floating gate transistors including floating and control gates, characterized by the steps of: forming a layer of floating gate material on a region of field oxide concurrently with a step of forming floating gates and forming first and second layers of control gate material over first and second portions of the layer of floating gate material, respectively, concurrently with the step of forming control gates, the first and second layers of control gate material serving as first and second capacitor electrodes, respectively.
Claim 44
Independent Claim
97 words
A method of forming an integrated circuit comprising field oxide regions, and a plurality of floating gate transistors including floating and control gates, characterized by the steps of: forming a layer of floating gate material on a region of field oxide concurrently with a step of forming floating gates and forming first and second layers of control gate material over first and second portions of the layer of floating gate material, respectively, concurrently with the step of forming control gates, the first and second layers of control gate material serving as first and second capacitor electrodes, respectively.
References Cited (Backward Citations)
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