EP0322665A2
Expired / Lapsed
EP
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Process for manufacturing CMOS integrated devices with reduced gate lengths
Assignee: STMicroelectronics SRL
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Filing: 1988-12-15
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Granted: —
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Expires: 2008-12-15
Abstract
Abstract A process for manufacturing CMOS integrated devices with gate lengths of less than one micron and high supply voltage is described. In order to improve the resistance of CMOS devices to breakdown and punch-through phenomena without cost increases with respect to conventional CMOS processes and limiting as much as possible the introduction of resistances in series to the transistors, less doped source and drain regions (31) being provided in only one of the two MOS transistors, e.g. in the N-channel transistor, to increase the breakdown voltage, an oppositely doped region (13′), e.g. with P-type doping, being provided around the source and drain regions (31) of this first transistor to protect this first transistor against punch-through, and doped wells (14) being provided around the source and drain regions (24) of the complementary transistor, which is e.g. a P-channel transistor; said doped wells (14) being oppositely doped with respect to said source and drain regions (24) but having a lower doping level than the region of the body (1) of semiconductor material which accommodates the complementary transistor, in order to increase the breakdown voltage of the P-channel complementary transistor.
Inventors
- 👤 Carlo Bergonzoni
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 06:56
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
327 words
Process for manufacturing a CMOS integrated device with reduced gate lengths, comprising the steps of: delimiting, in a body (1) of semiconductor material having a larger surface and defining at least one first region (2) with a first type of conductivity, which has a first level of doping impurities to produce a first MOS transistor with a first type of channel, and a second region (3) with a second type of conductivity opposite to the first one, having a second level of doping impurities to provide a second MOS transistor complementary to the first transistor; defining active areas (6,7) intended to accommodate said MOS transistors in said first region (2) and said second region (3); growing an insulating layer (8) on said larger surface; selectively forming gate regions (10,11) in semiconductor material on said insulating layer (8) at said active regions (6,7); selectively forming source and drain regions (31) with said second type of conductivity for the first transistor in said first region (2) and of source and drain regions (24) with said first type of conductivity for the second transistor in said second (3) region of the body (1) of semiconductor material; defining contacts and interconnection lines; characterized in that after said step of selectively forming gate regions, a first step of introducing doping impurities (12) is performed on the entire larger surface of said body of semiconductor material, said doping impurities (12) being adapted to impart said first type of conductivity to provide first wells (13) with said first type of conductivity around the source and drain regions (31) of said first transistor in said first region (2) and second wells (14) with said second type of conductivity around the source and drain regions (24) of said second transistor in said second region (3), said first wells (13) having a higher level of doping impurities than said first level and said second wells (14) having a lower level of doping impurities than said second level.
Claim 2
Dependent Claim
327 words
Process for manufacturing a CMOS integrated device with reduced gate lengths, comprising the steps of: delimiting, in a body (1) of semiconductor material having a larger surface and defining at least one first region (2) with a first type of conductivity, which has a first level of doping impurities to produce a first MOS transistor with a first type of channel, and a second region (3) with a second type of conductivity opposite to the first one, having a second level of doping impurities to provide a second MOS transistor complementary to the first transistor; defining active areas (6,7) intended to accommodate said MOS transistors in said first region (2) and said second region (3); growing an insulating layer (8) on said larger surface; selectively forming gate regions (10,11) in semiconductor material on said insulating layer (8) at said active regions (6,7); selectively forming source and drain regions (31) with said second type of conductivity for the first transistor in said first region (2) and of source and drain regions (24) with said first type of conductivity for the second transistor in said second (3) region of the body (1) of semiconductor material; defining contacts and interconnection lines; characterized in that after said step of selectively forming gate regions, a first step of introducing doping impurities (12) is performed on the entire larger surface of said body of semiconductor material, said doping impurities (12) being adapted to impart said first type of conductivity to provide first wells (13) with said first type of conductivity around the source and drain regions (31) of said first transistor in said first region (2) and second wells (14) with said second type of conductivity around the source and drain regions (24) of said second transistor in said second region (3), said first wells (13) having a higher level of doping impurities than said first level and said second wells (14) having a lower level of doping impurities than said second level.
Claim 3
Dependent Claim
82 words
Process according to claim 1, characterized in that after said first step of introducing doping impurities (12), a second step (18) of lightly introducing further doping impurities is performed on the entire surface of said body (1) of the semiconductor material, said doping impurities being adapted to impart said second type of conductivity, to provided scarcely doped regions (19) with said second type of conductivity adjacent to said drain and source regions (31) of said first transistor in said first region (2).
Claim 4
Dependent Claim
105 words
Process according to the preceding claims, characterized in that said step of selectively forming source and drain regions (24,31) comprises: the selective introduction of doping impurities (23) adapted to impart said first type of conductivity to said second region (3), laterally the gate region (11) of said second transistor, the provision of spacer structures (27) of insulating material laterally to the gate regions (10) of said first transistor and the selective introduction of doping impurities (30) adapted to impart said second type of conductivity to said first region (2), laterally to said gate region (10) and to said spacer structures (27) of said first transistor.
Claim 5
Dependent Claim
76 words
Process according to one or more of the preceding claims, characterized in that said areas (6), regions (10,31) and wells (13) with said first type of conductivity are of the P type, said areas (7), regions (11,24) and wells (14) with said second type of conductivity are of the N type, said first MOS transistor is of the N-channel type with lightly doped drain regions (31), and said second MOS transistor is of the P-channel type.
Claim 6
Dependent Claim
75 words
Process according to one or more of claims 1-3, characterized in that said areas (6), regions (31,10) and wells (13) with said first type of conductivity are of the N type, said areas (7), regions (24,11) and wells (14) with said second type of conductivity are of the P type, said first MOS transistor is of the P-channel type with lightly doped drain regions (31), and said second MOS transistor is of the N-channel type.
Claim 7
Dependent Claim
199 words
CMOS device with reduced channel lengths, comprising a body (1) in semiconductor material having a larger surface and defining at least one first region (2) with a first type of conductivity which has a first level of doping impurities and accommodates source and drain regions (31) of a first MOS transistor with a first channel type, said source and drain regions having a second type of conductivity opposite to said first type conductivity, and a second region (3) with a second type of conductivity which has a second level of doping impurities and accommodates source and drain regions with said first type of conductivity of a second MOS transistor complementary to the first one, characterized in that it comprises first wells (13) with a first type of conductivity surrounding said source and drain (31) regions of said first transistor in said first region (2) and second wells (14) with said second type of conductivity, surrounding said source and drain regions (24) of said transistor, in said second region (3), said first wells (13) having a higher level of doping than said first level and said second wells (14) having a lower level of doping impurities than said second level.
Claim 8
Dependent Claim
199 words
CMOS device with reduced channel lengths, comprising a body (1) in semiconductor material having a larger surface and defining at least one first region (2) with a first type of conductivity which has a first level of doping impurities and accommodates source and drain regions (31) of a first MOS transistor with a first channel type, said source and drain regions having a second type of conductivity opposite to said first type conductivity, and a second region (3) with a second type of conductivity which has a second level of doping impurities and accommodates source and drain regions with said first type of conductivity of a second MOS transistor complementary to the first one, characterized in that it comprises first wells (13) with a first type of conductivity surrounding said source and drain (31) regions of said first transistor in said first region (2) and second wells (14) with said second type of conductivity, surrounding said source and drain regions (24) of said transistor, in said second region (3), said first wells (13) having a higher level of doping than said first level and said second wells (14) having a lower level of doping impurities than said second level.
References Cited (Backward Citations)
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