Intermediate potential generation circuit for generating a potential intermediate between a power source potential and ground potential

Claim 2

In an intermediate potential generation circuit for outputting at an output node (14,16, 18, 20, 23) an intermediate potential (VM) intermediate between a first power source potential (VCC, GND) and a second power source potential, the improvement which comprises: reference potential generating means (40,50) for generating first and second reference potentials responsive to the first and second power source potentials, wherein the first reference potential is lower than the second reference potential; comparing means (41,42, 43, 44, 51) responsive to the fist reference potential, the second reference potential and the intermediate potential for producing first control signal when the intermediate potential is lower than the first reference potential, and for producing second control signal when the intermediate potential is higher than the second reference potential; first circuit means (M9,M15) having an output connected to said output node and an input responsive to the fist control signal for raising the intermediate potential and second circuit means (M10,M22) having an output connected to said output node and an input responsive to the second control signal for lowering the intermediate potential at said output node.

Claim 3

The intermediate potential generation circuit of claim 1, wherein the potential difference across the input and the output of respective of said first and second output circuit means upon production of respective of said first and second control signals is the difference between one of said power source potentials and said intermediate potential.

Claim 4

The intermediate potential generation circuit of claim 1, wherein the comparing means (41, 42, 43, 44, 51) comprises: first and second comparators (CMP1, CMP2, CMP3, CMP6) responsive to the power source potential, wherein the first comparator outputs the first control signal in response to the first reference potential and the intermediate potential, and the second comparator outputs the second control signal in response to the second reference potential and the intermediate potential.

Claim 5

The intermediate potential generation circuit of claim 1, wherein the first and the second circuit means each includes a P -channel MOS transistor (M9, M10) having a gate electrode supplied with a respective of the first and second control signals and a selected of a drain and a source connected to said output node.

Claim 6

The intermediate potential generation circuit according to claim 4, wherein tbe gate to source potential of the P -channel MOS transistors of said first and second circuit means upon application of respective of said fist and second control signals to said P -channel MOS transistors is the diffetence beteween one of said power source potentials and said intermediate potential.

Claim 7

The intermediate potential genetration circuit of claim 1, wherein the reference potential generating means comprising: a first path between the first power source potential and second power source potential, including; a first resistor (R6) having a first end supplied with the first power source potential, and a second end, a first MOS transistor (M5) of first conductivity type having a gate electrode and a drain electrode connected to the other end of the first resistor, and a source electrode, a second MOS transistor (M6) of a second conductivity type, having a source electrode connected to the source electrode of the first MOS transistor, and a gate electrode and a drain electrode connected in common, and a second resistor (R7) having a first end connected to the common connection of the gate and the drain electrodes of the second MOS transistor, and a second end supplied with the second power source potential, a second path between the first power source potential and the second power source potential, including; a third MOS transitor (M7) of first conductivity having a drain electrode supplied with the first power source potential, and a gate electrode connected to the drain electrode of the first MOS transistor, and a source electode, and a third resistor (R8) having a first end connected to the source electrode of the third MOS transistor, and a second end supplied with the second power source potential, and a third path between the first power source potential and the second power source potential, including; a fourth resistor (R9) having first end supplied with the first power source potential, and a second end, and a fourth MOS transistor (M8) of second conductivity type having a gate electrode connected to the drain electrode of the second MOS transistor, a source electrode connected to the second end of the fourth resistor and a drain electrode supplied with the second power source potential.

Claim 8

The intermediate potential generation circuit of claim 3, wherein the first comparator has a non-inverting input terminal supplied with the first reference potential and an inverting input terminal supplied with the intermediate potential, and the second comparator has an inverting input terminal supplied with the second reference potential, and a non-inverting input terminal supplied with the intermediate potential.

Claim 9

The intermediate potential generation circuit of claim 3, wherein the first comparator has an inverting input terminal supplied with the first reference potential and a non-inverting input terminal supplied with the intermediate potential, and the second comparator has an inverting input terminal supplied with the second reference potential and a non-inverting input terminal supplied with the intermediate potential.

Claim 10

The intermediate potential generation circuit of claim 3, wherein the first comparator (CMP1) has a non-­inverting input terminal supplied with the first reference potential and an inverting input terminal supplied with the intermediate potential, and the second comparator (CMP2) has a non-inverting input terminal supplied with the second refence potential and an inverting input terminal supplied with the intermediate potential.

Claim 11

The intermediate potential generation circuit of claim 3, wherein the first comparator (CMP3) has an inverting input terminal supplied with the first reference potential, and a non-inverting input terminal supplied with the intermediate potential, and the second comparator (CMP6) has a non-inverting input terminal supplied with the second reference potential and an inverting input terminal supplied with the intermediate potential.

Claim 12

The intermediate potential generation circuit of claim 3, wherein the reference potential generating means includes a plurality of resistors (R22, R23, R24, R25) connected in series between the first and second power source potentials.