Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
217 words
A driver circuit comprising: an input terminal (11) receiving a digital input signal; an output terminal (14); a first supply voltage terminal (3) for receiving a first supply voltage; a second supply voltage terminal (5) for receiving a second supply voltage; a third supply voltage terminal (4); a fourth supply voltage terminal (6) ; first means (1, 2, 12) coupled between said first and second supply voltage terminals for dividing the voltage difference between said first and second supply voltages and providing third and fourth supply voltages at said third and fourth supply voltage terminals, respectively; second means (8, 12) coupled between said third and fourth supply voltage terminals and to said input terminal for inverting said input signal; third means (13, 16) coupled between said first and second supply voltage terminals and to said output terminal for providing a digital output signal; fourth means (18, 19) coupled between said first and second supply voltage terminals and coupled to both said third means and said second means for biasing said third means in response to said inverted input signal; and fifth means (21, 22) coupled between said first and second supply voltage terminals and coupled to both said fourth means and said input terminal for sourcing current to said fourth means in response to said input signal.
Claim 2
Dependent Claim
217 words
A driver circuit comprising: an input terminal (11) receiving a digital input signal; an output terminal (14); a first supply voltage terminal (3) for receiving a first supply voltage; a second supply voltage terminal (5) for receiving a second supply voltage; a third supply voltage terminal (4); a fourth supply voltage terminal (6) ; first means (1, 2, 12) coupled between said first and second supply voltage terminals for dividing the voltage difference between said first and second supply voltages and providing third and fourth supply voltages at said third and fourth supply voltage terminals, respectively; second means (8, 12) coupled between said third and fourth supply voltage terminals and to said input terminal for inverting said input signal; third means (13, 16) coupled between said first and second supply voltage terminals and to said output terminal for providing a digital output signal; fourth means (18, 19) coupled between said first and second supply voltage terminals and coupled to both said third means and said second means for biasing said third means in response to said inverted input signal; and fifth means (21, 22) coupled between said first and second supply voltage terminals and coupled to both said fourth means and said input terminal for sourcing current to said fourth means in response to said input signal.
Claim 3
Dependent Claim
44 words
The driver circuit according to claim 1 wherein said fifth means comprises complimentary bipolar transistors (21, 22) having their collectors coupled to said first and second supply voltage terminals, respectively, their emitters coupled to said thickness and their bases coupled to said second means.
Claim 4
Dependent Claim
45 words
The driver circuit according to claim 2 wherein said fourth means comprises second complimentary MOS transistors (18, 19) having their sources coupled to said first and second supply voltage terminals, respectively, their drains coupled to said thickness and their gates coupled to said input terminal.
Claim 5
Dependent Claim
154 words
A driver circuit comprising: a first voltage terminal (3); a second voltage terminal (5); an input terminal (11) an output terminal (14); a first bipolar transistor (13) having its collector-emitter current path coupled between said first voltage terminal and said output terminal, and a base; a second bipolar transistor (16) having its collector-emitter current path coupled between said output terminal and said second voltage terminal, and a base; first means (8, 12) coupled between said first and second voltage terminals and to said input terminal for inverting an input signal; second means (21, 22) coupled between said first and second voltage terminals and between said first means and said bases of said first and second bipolar transistors for biasing said first and second bipolar transistors in response to said inverted input signal; and third means (18, 19) coupled between said first and second voltage terminals and to said second means for sourcing current thereto.
Claim 6
Dependent Claim
154 words
A driver circuit comprising: a first voltage terminal (3); a second voltage terminal (5); an input terminal (11) an output terminal (14); a first bipolar transistor (13) having its collector-emitter current path coupled between said first voltage terminal and said output terminal, and a base; a second bipolar transistor (16) having its collector-emitter current path coupled between said output terminal and said second voltage terminal, and a base; first means (8, 12) coupled between said first and second voltage terminals and to said input terminal for inverting an input signal; second means (21, 22) coupled between said first and second voltage terminals and between said first means and said bases of said first and second bipolar transistors for biasing said first and second bipolar transistors in response to said inverted input signal; and third means (18, 19) coupled between said first and second voltage terminals and to said second means for sourcing current thereto.
Claim 7
Dependent Claim
47 words
The driver circuit according to claim 4 further comprising fourth means (1, 2, 7) coupled between said first and second voltage terminals for providing a supply voltage substantially equal in magnitude to the magnitude of the voltage swing of an output signal appearing on said output terminal.
Claim 8
Dependent Claim
77 words
The driver circuit according to claim 4 wherein said second means comprises: a third bipolar transistor (21) having its collector-emitter current path coupled between said first voltage terminal and said base of said second bipolar transistor, and a base coupled to said first means; and a fourth bipolar transistor (22) having its collector-emitter current path coupled between said base of said second bipolar transistor and said second voltage terminal, and a base coupled to said first means.
Claim 9
Dependent Claim
75 words
The driver circuit according to claim 6 wherein said third means comprises: a first MOS transistor (18) having its source-drain path coupled between said first voltage terminal and said base of said first bipolar transistor, and a gate coupled to said input terminal; and a second MOS transistor (19) having its source-drain path coupled between said base of said second bipolar transistor and said second voltage terminal, and a gate coupled to said input terminal.
Claim 10
Dependent Claim
47 words
The driver circuit according to claim 7 further comprising fourth means (1, 2, 7) coupled between said first and second voltage terminals for providing a supply voltage substantially equal in magnitude to the magnitude of the voltage swing of an output signal appearing on said output terminal.
Claim 11
Dependent Claim
158 words
A driver circuit comprising: a first voltage terminal (3); a second voltage terminal (5); an input terminal (11) for receiving an input signal having first and second states; an output terminal (14); a first bipolar transistor (13) having its collector-emitter current path coupled between said first voltage terminal and said output terminal, and a base; a second bipolar transistor (16) having its collector-emitter current path coupled between said output terminal and said second voltage terminal, and a base; and first means (8, 12, 18, 19, 21, 22) coupled between said first and second voltage terminals and between said input terminal and said bases of said first and second bipolar transistors for actively biasing said first bipolar transistor on and said second bipolar transistor off in response to said first state of said input signal and actively biasing said first bipolar transistor off and said second bipolar transistor on in response to said second state of said input signal.
Claim 12
Dependent Claim
158 words
A driver circuit comprising: a first voltage terminal (3); a second voltage terminal (5); an input terminal (11) for receiving an input signal having first and second states; an output terminal (14); a first bipolar transistor (13) having its collector-emitter current path coupled between said first voltage terminal and said output terminal, and a base; a second bipolar transistor (16) having its collector-emitter current path coupled between said output terminal and said second voltage terminal, and a base; and first means (8, 12, 18, 19, 21, 22) coupled between said first and second voltage terminals and between said input terminal and said bases of said first and second bipolar transistors for actively biasing said first bipolar transistor on and said second bipolar transistor off in response to said first state of said input signal and actively biasing said first bipolar transistor off and said second bipolar transistor on in response to said second state of said input signal.
Claim 13
Dependent Claim
177 words
The driver circuit according to claim 9 wherein said first means comprises: second means (8, 12) coupled between said first and second voltage terminals and between said input terminal and said first means for inverting said input signal; a third bipolar transistor (21) having its collector-emitter current path coupled between said first voltage terminal and said base of said second bipolar transistor, and a base coupled to said second means for receiving said inverted input signal; a fourth bipolar transistor (22) having its collector-emitter current path coupled between said base of said second bipolar transistor and said second voltage terminal, and a base coupled to said second means for receiving said inverted input signal; a first MOS transistor (18) having its source-drain path coupled between said first voltage terminal and said base of said first bipolar transistor, and a gate coupled to said input terminal; and a second MOS transistor (19) having its source-drain path coupled between said base of said second bipolar transistor and said second voltage terminal, and a gate coupled to said input terminal.