EP0318270A2
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EP
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A multiprocessor system and corresponding method
Assignee: Fujitsu Ltd
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Filing: 1988-11-23
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Granted: —
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Expires: 2008-11-23
Abstract
Abstract Processors (CPU1, ... CPUn) constituting a multiprocessor system are divided into a plurality of clusters (1, 2, 3...m) of processors. The state of a cluster (1, 2, 3...m) is based on the state of processors belonging to that cluster, an order is set for each cluster (1, 2, 3, ...m), and then the processors belonging to that cluster are controlled based on the order of that cluster.
Inventors
- 👤 Masayuki Eshiiru Nakahara 404 Ikeda
- 👤 Koichi Ueda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 17:07
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/177; G06F15/163; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
66 words
A method of control between processors constituting a multiprocessor system comprising the steps of: dividing a plurality of processors constituting the multiprocessor system into a plurality of clusters; defining a state of a cluster based on a state of a processor belonging to that cluster; setting an order to that cluster; and, controlling a processor belonging to that cluster based on the order to that cluster.
Claim 2
Independent Claim
66 words
A method of control between processors constituting a multiprocessor system comprising the steps of: dividing a plurality of processors constituting the multiprocessor system into a plurality of clusters; defining a state of a cluster based on a state of a processor belonging to that cluster; setting an order to that cluster; and, controlling a processor belonging to that cluster based on the order to that cluster.
Claim 3
Dependent Claim
29 words
A method as claimed in claim 1, wherein said state of each processor is defined by four states of STOP, OPERATION, LOAD and CHECK-STOP, these four states being exclusive.
Claim 4
Dependent Claim
44 words
A method as claimed in claim 1 or 2, wherein said state of each cluster is defined by three states of CLUSTER-STOP, CLUSTER-CHECK-STOP, and SUBSYSTEM-DAMAGE, each of these three states being based on any one or more of said four states of the processor.
Claim 5
Dependent Claim
38 words
A method as claimed in claim 3, wherein said CLUSTER-STOP is defined by a state in which none of the processors is in the OPERATION and LOAD state and at least one processor is in the STOP state.
Claim 6
Dependent Claim
36 words
A method as claimed in claim 3 or 4, wherein said CLUSTER-CHECK-STOP is defined by a state that none of the processors is connected to another processor and none of the processors is supplied with power.
Claim 7
Dependent Claim
27 words
A method as claimed in claim 3, 4 or 5, wherein said SUBSYSTEM-DAMAGE is defined by the states in which the cluster recognizes damage to the subsystem.
Claim 8
Independent Claim
25 words
A method as claimed in any preceding claim, wherein said order comprises a CSIGP order constituted by a SENSE order, a CLUSTER-order and a parameter.
Claim 9
Dependent Claim
25 words
A method as claimed in claim 7, wherein said CSIGP order further comprises a CLUSTER-SENSE order, a CLUSTER-SYNCHRONOUS-CALL order and a CLUSTER-RESET and LOAD order.
Claim 10
Dependent Claim
22 words
A method as claimed in claim 7 or 8, wherein said GSIGP order further comprises a CLUSTER-BROADCAST-INTERRUPTION order and a CLUSTER-ASYNCHRONOUS-INTERRUPTION order.
Claim 11
Independent Claim
110 words
An apparatus for a cluster control between processors (CPU1,... CPUn) constituting a multiprocessor system, processors (CPU1,....CPUn) being divided into a plurality of clusters (1, 2, 3,...,m) the apparatus comprising: a global control unit (GCU) connected to each of the clusters (1, 2, 3,...m) through a corresponding bus line and processing an order between the clusters, and a memory control unit (MCU1, ... MCUM) provided in each of the clusters and connected between the global control unit (GCU) and each of the processors (CPU1-CPU3) belonging to each of the clusters (1, 2, 3,... m) and controlling transmission and reception of orders between the global control unit (GCU) and the processors (CPU1,...CPUm).
Claim 12
Independent Claim
110 words
An apparatus for a cluster control between processors (CPU1,... CPUn) constituting a multiprocessor system, processors (CPU1,....CPUn) being divided into a plurality of clusters (1, 2, 3,...,m) the apparatus comprising: a global control unit (GCU) connected to each of the clusters (1, 2, 3,...m) through a corresponding bus line and processing an order between the clusters, and a memory control unit (MCU1, ... MCUM) provided in each of the clusters and connected between the global control unit (GCU) and each of the processors (CPU1-CPU3) belonging to each of the clusters (1, 2, 3,... m) and controlling transmission and reception of orders between the global control unit (GCU) and the processors (CPU1,...CPUm).
Claim 13
Dependent Claim
72 words
An apparatus as claimed in claim 10, wherein each of the clusters (1, 2, 3, ...m) further comprises a local storage unit (LSU) connected to the memory control unit (MCU) and storing data, a direct access storage device (DASD) connected to the memory control unit (MCU) and storing data, and a service processor (SVP) connected to the memory control unit (MCU) and processing the reset operation and an initial program loading operation.
Claim 14
Dependent Claim
104 words
An apparatus as claimed in claim 10 or 11, wherein the global control unit (GCU) comprises a priority circuit (PRT) for determining a priority of the order sent from each of the clusters (1, 2, 3, ...m) a logical-to-real cluster translation logic circuit (LRCL) for converting a logical cluster number to a physical cluster number, a logical-to-real cluster translation tabel (LRCT) for referring to a relationship between the logical cluster number and the physical cluster number, a cluster connection table (CCNT) for indicating a connection state of the cluster, and a cluster power-ON table (CPON) for indicating a power ON/OFF state of the cluster.
Claim 15
Dependent Claim
78 words
An apparatus as claimed in claim 10, 11 or 12, wherein the memory control unit comprises a priority circuit (PRT) for determining a priority of requests sent from the processors (CPU1...CPUn) a command executor (COEX) for executing a request sent from the global control unit (GCU), a status generator (SGE) for generating status information in accordance with a request from the command executor (COEX), and an interruption pending latch circuit (ITPL) for turning ON an interruption pending latch.
References Cited (Backward Citations)
No citation records indexed.
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