Semiconductor memory device having a charge barrier layer and method for producing the same

Claim 1

A semiconductor memory device comprising a semiconductor substrate (11) having source and drain regions (16, 17) each having a conduction type opposite to that of the semiconductor substrate (11); an insulation film (13) formed on a main surface of the semiconductor substrate (11) having first and second contact windows (30, 31); and a gate electrode (14₁) formed on the insulation film (13) so as to be located between the source and drain regions (16, 17), the semiconductor substrate (11) having a charge barrier layer (15) which has the same conduction type as the semiconductor substrate (11) and has an impurity concentration higher than that of the semiconductor substrate (11), characterized in that the charge barrier layer (15) is formed so that a depth (d₁) of the charge barrier layer (15) located under the gate electrode (14₁) measured from the main surface of the semiconductor substrate (11) is smaller than a depth (d₂) of the charge barrier layer (15) located under the source and drain regions (16, 17) measured from the main surface of the semiconductor substrate (11).

Claim 8

A method of producing a semiconductor memory device, characterized by comprising the steps of forming an insulation film (13) on a main surface of a semiconductor substrate (11); forming a gate electrode (14₁) on the insulation film (13), the gate electrode (14₁) having the conduction type opposite to that of the semiconductor substrate (11); implanting first impurity ions into the semiconductor substrate (11) through the entire main surface thereof, the first impurity ions having a conduction type (p⁺-type) identical to that of the semiconductor substrate (p-type) and having an impurity concentration higher than that of the semiconductor substrate (11), whereby the charge barrier layer (15) is formed so that a depth (d₁) of the charge barrier layer (15) located under the gate electrode (14₁) measured from the main surface of the semiconductor substrate (11) is smaller than a depth (d₂) of the charge barrier layer (15) located under source and drain regions (16, 17) measured from the main surface of the semiconductor substrate (11); and implanting second impurity ions into the semiconductor substrate (11) so as to form the source and drain regions (16, 17) located on both sides of the gate electrode (11), the second impurity ions having the conduction type opposite to that of the first impurity ions.

Claim 9

A method of producing a semiconductor memory device, characterized by comprising the steps of forming an insulation film (13) on a main surface of a semiconductor substrate (11); forming a gate electrode (14₁) on the insulation film (13), the gate electrode (14₁) having the conduction type opposite to that of the semiconductor substrate (11); implanting first impurity ions into the semiconductor substrate (11) through the entire main surface thereof, the first impurity ions having a conduction type (p⁺-type) identical to that of the semiconductor substrate (p-type) and having an impurity concentration higher than that of the semiconductor substrate (11), whereby the charge barrier layer (15) is formed so that a depth (d₁) of the charge barrier layer (15) located under the gate electrode (14₁) measured from the main surface of the semiconductor substrate (11) is smaller than a depth (d₂) of the charge barrier layer (15) located under source and drain regions (16, 17) measured from the main surface of the semiconductor substrate (11); and implanting second impurity ions into the semiconductor substrate (11) so as to form the source and drain regions (16, 17) located on both sides of the gate electrode (11), the second impurity ions having the conduction type opposite to that of the first impurity ions.