EP0317159A2
Expired / Lapsed
EP
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Clock recovery arrangement
Assignee: AT&T Inc
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Filing: 1988-11-09
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Granted: —
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Expires: 2008-11-09
Abstract
Abstract A digital clock recovery arrangement includes a (16,14) reference clock which provides a plurality of N signals with different clock phases. The incoming data stream is sampled and clocked with the reference clock to generate a plurality of M samples for each data bit (RD1, RD2, RD3). The logic values of the M samples are then analyzed (in 20) to determine the relationship between the current clock phase and the data bit transition. In particular, if all samples agree, the clock phase is correctly aligned with the data. If the clock phase is either leading or lagging the data, various samples will disagree. In the latter situation, the clock phase is adjusted until all samples agree, the particular clock which provides this state thus being defined as the recovered clock signal.
Inventors
- 👤 Ernest Eisenhardt Bergmann
- 👤 Sherre Marie Staves
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 07:24
CPC Classifications
H; H04; H04L; H04L5/00; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H03; H03D; H03D3/00; H03D3/02; H03D3/24; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/085; H03L7/091; H04L7/0079; H04L7/0083
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
178 words
A clock recovery arrangement for generating from an incoming digital data stream a retimed data output signal and a recovered clock signal, said arrangement comprising a data input line (D) for reception of the incoming data stream, and characterised by data sampling means (12,18) coupled to the data input line for producing in dependence upon the recovered clock signal a plurality of M clocked samples (RD1,RD2,RD3) of each data bit from said incoming data stream, M being at least equal to three, one clocked sample being located at the approximate midpoint of the data bit and defined as the retimed data output of said clock recovery arrangement, at least one clocked sample being located before the midpoint, and at least one other clocked sample being located after the midpoint, means (16,14,22) for generating the recovered clock signal having a predetermined frequency and adjustable phase, and clock phase decision means (20) for comparing the logic values of said plurality of M clocked samples and adjusting the phase of the recovered clock signal if all do not agree in value.
Claim 2
Dependent Claim
178 words
A clock recovery arrangement for generating from an incoming digital data stream a retimed data output signal and a recovered clock signal, said arrangement comprising a data input line (D) for reception of the incoming data stream, and characterised by data sampling means (12,18) coupled to the data input line for producing in dependence upon the recovered clock signal a plurality of M clocked samples (RD1,RD2,RD3) of each data bit from said incoming data stream, M being at least equal to three, one clocked sample being located at the approximate midpoint of the data bit and defined as the retimed data output of said clock recovery arrangement, at least one clocked sample being located before the midpoint, and at least one other clocked sample being located after the midpoint, means (16,14,22) for generating the recovered clock signal having a predetermined frequency and adjustable phase, and clock phase decision means (20) for comparing the logic values of said plurality of M clocked samples and adjusting the phase of the recovered clock signal if all do not agree in value.
Claim 3
Dependent Claim
61 words
An arrangement as claimed in claim 1 comprising clock monitoring means (24) responsive to the recovered clock signal for generating as an output a reset signal when said recovered clock signal is not present, the clock phase decision means being responsive to the reset signal to provide a predetermined phase of clock signal, regardless of the values of the clocked samples.
Claim 4
Dependent Claim
17 words
An arrangement as claimed in claim 2 wherein the clock monitoring means comprises an analog timing circuit.
Claim 5
Dependent Claim
17 words
An arrangement as claimed in claim 2 wherein the clock monitoring means comprises a digital timing circuit.
Claim 6
Dependent Claim
48 words
An arrangement as claimed in claim 1, 2, 3 or 4 wherein the clock phase decision means comprises programmable logic array means responsive to the plurality of M clocked samples for generating as an output a phase decision signal for adjusting the phase of the recovered clock signal.
Claim 7
Dependent Claim
43 words
An arrangement as claimed in claim 5 wherein the programmable logic array means is responsive to an external hold control signal to maintain the recovered clock signal at a predetermined clock phase regardless of the values of the plurality of M clocked samples.
Claim 8
Dependent Claim
47 words
An arrangement as claimed in claim 5 or 6 wherein the programmable logic array means is responsive to an external force control signal to adjust the recovered clock signal through a predetermined series of clock phases regardless of the values of the plurality of M clocked samples.
Claim 9
Dependent Claim
78 words
An arrangement as claimed in any preceding claim wherein the data sampling means comprises an M-length tapped delay line (12) responsive to the incoming digital data stream for producing as parallel outputs a plurality of M sampled data bits, and a plurality of M latches (18), each latch being responsive to a respective one of the plurality of M sampled data bits and the recovered clock signal for producing as an output the plurality of M clocked samples.
Claim 10
Dependent Claim
108 words
An arrangement as claimed in any one of claims 1 to 7 comprising means (38) for generating a plurality of M clock signals, one clock signal comprising the recovered clock signal, X clock signals comprising clock phases lagging the recovered clock signal (X<M), and M-1-X clock signals comprising clock phases leading the recovered clock signal, and wherein the data sampling means comprises a plurality of M clocked latches (32,34,36) responsive to the incoming digital data stream, each latch being responsive to a respective one of the plurality of M clock signals, said plurality of M latches serving to produce as an output the plurality of M clocked samples.
Claim 11
Dependent Claim
82 words
An arrangement as claimed in any preceding claim wherein the means for generating the recovered clock signal comprises clock means (16) for generating a reference clock signal at the predetermined frequency, means (14) for deriving from the reference clock signal a plurality of N clock signals at the predetermined frequency, adjacent clock signals being separated in phase by 360°/N, and means (22) controlled by the clock phase decision means for selecting one of the N clock signals as the recovered output signal.
Claim 12
Dependent Claim
10 words
An arrangement as claimed in any preceding claim wherein M=3.
Claim 13
Dependent Claim
57 words
An arrangement as claimed in claim 10 wherein M>3, and the clock phase decision means serves to control the selecting means to adjust the phase of the recovered clock signal by more than one clock phase separation at a time as a function of the location of the change in logic value between adjacent data bit samples.
References Cited (Backward Citations)
No citation records indexed.
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